QSC KW153 IRS20957 Not Starting, Both HO/LO Low, Troubleshooting UVLO, CSD, FAULT, Bootstrap

User question

qsc kw153 irs20957 not starting up

Artificial Intelligence Response

Direct answer to the question

• If both HO and LO from the IRS20957/IRS20957S are stuck low in a QSC KW153, the driver is almost certainly being held off by a protection/UVLO condition or an external shutdown (CSD) command. The most common root causes are: missing/low VCC to the driver, CSD held low by the module’s protection supervisor, latched FAULT (typically from over‑current sensing or shorted output FETs), or a broken bootstrap path.
• Key points
  • Verify VCC to the IRS20957 is within spec and stable; UVLO will clamp both outputs low.
  • Confirm the driver’s internal 5 V reference (VREF) is present; if absent, the IC is bad or unpowered.
  • Check that CSD (shutdown/reset) is high; if low, something upstream is intentionally disabling the driver.
  • If FAULT is asserted low, find and clear the underlying OCP/OTP cause (often shorted output MOSFETs or sense/OCSET network faults).
  • Inspect bootstrap diode/cap and the low‑side path; without a first low‑side conduction, VB–VS will never charge.

Detailed problem analysis

• Architecture recap (so we troubleshoot the right things)
  • IRS20957/IRS20957S is a high‑voltage half‑bridge MOSFET gate driver with integrated protection and a 5 V VREF. It drives external MOSFETs (it is not a complete power stage). The KW153 uses it in a self‑oscillating Class‑D loop; if the loop can’t start or protection is active, HO/LO remain low.
• Signals/pins that decide “start” vs “no start”
  • VCC: Logic/gate-drive supply (typically 10–15 V). If below UVLO threshold, both HO/LO are forced low.
  • VREF (~5.0 V): Generated by the IC; used to bias DT/OCSET and often as logic pull‑up. Missing/unstable VREF points to a dead IC or bad decoupling.
  • CSD (shutdown/reset): Must be above its high threshold (≈2 V+) for run; external protection logic (DC detect, thermal, rail supervisor, MCU) frequently pulls CSD low to hold the driver off or to time the auto‑reset after a fault.
  • FAULT (open‑drain output): When low, indicates an internal protection event (e.g., over‑current). With FAULT low, HO/LO are held off until the CSD timing/reset sequence completes.
  • IN+/IN−: Comparator inputs for the self‑oscillating loop. If the feedback network is open/misbiased or inputs are railed, oscillation may not commence even with CSD high.
  • DT, OCSET: If DT or OCSET networks go open/short or are way out of value, the driver may either never switch or immediately trip OCP.
  • VB–VS (bootstrap): Must charge to roughly VCC to enable the first high‑side turn‑on. A failed bootstrap diode/cap, or a low‑side that never turns on, prevents high‑side switching.
• What “both HO/LO low” typically means in practice
  • UVLO on VCC (or on VB–VS once running), CSD asserted low, FAULT latched due to OCP/OTP, or a comparators/loop condition that prevents the first low‑side conduction. A hard shorted output MOSFET or shorted output filter can also cause immediate FAULT/OCP and hold both outputs low.
• Common KW‑series field failures relevant to this symptom
  • Shorted half‑bridge MOSFET(s) and blown/open gate resistors/snubber parts.
  • Failed bootstrap diode or dried‑out bootstrap/local decoupling electrolytics.
  • Damaged OC sense network (open/shifted sense resistors, cracked SMDs) that makes OCSET effectively “too low,” tripping OCP at idle.
  • Protection controller holding the amp in shutdown because another rail (±15 V analog, +5 V logic, PFC/HV rails) is missing or out of tolerance.
  • Counterfeit/used driver ICs with weak VREF or CSD/FAULT behavior.

Current information and trends

• Technically current points to emphasize
  • IRS-class audio drivers remain widely used; counterfeit parts have become a frequent repair trap—symptoms include unstable VREF, excessive quiescent current, or failing under bootstrap load.
  • Many manufacturers (including in newer revisions) migrate to higher‑integration Class‑D power stages with digital control, which reduces field failures in the discrete driver/MOSFET support network but increases module‑level replacement over component‑level repair.

Supporting explanations and details

• Why bootstrap matters the very first microseconds
  • The high‑side supply (VB–VS) is charged only when the low‑side device conducts and lifts current through the bootstrap diode into the cap. If CSD is low or UVLO prevents LO from ever turning on, VB–VS stays ~0 V and HO can never start, making “both low” a self‑consistent symptom even if the high‑side section is healthy.
• Over‑current sense path failure mode
  • If OCSET sees an abnormally low threshold (open divider, wrong value, flux residue leakage), the IC can interpret normal bias currents as over‑current and instantly pull FAULT low, keeping HO/LO off and attempting periodic auto‑resets via CSD timing.
• Self‑oscillating loop non‑start
  • Broken feedback network (open output LC feedback resistor/cap, cracked solder) or IN+/IN− biased at a rail may stall the loop. Many designs include a “start‑bias” or pulldown so the low‑side turns on first to kick the bootstrap; if that bias path opens, startup can fail.

Ethical and legal aspects

• Safety: The KW153’s mains PFC SMPS and HV rails are lethal. Use an isolation transformer, differential probes, current‑limited bench supplies, and proper PPE. Discharge bulk capacitors before ohmmeter checks.
• Compliance: Do not bypass protection permanently (e.g., forcing CSD high) when returning equipment to service. Ensure post‑repair leakage, ground continuity, and HiPot tests meet safety standards.

Practical guidelines

• Fast, safe decision tree (DMM first, scope second) 1) Power off, discharge rails. Measure output MOSFETs D–S for shorts; check gate resistors/snubber parts. Repair any hard shorts before applying power. 2) Power up with a series bulb/variac or current‑limited mains input. With COM as reference:
  • VCC: expect ≈12–15 V steady. If <UVLO, troubleshoot the low‑voltage supply/regulator and its decoupling.
  • VREF: ≈5.0 V. If missing or noisy, suspect the IC or local decoupling.
  • CSD: must be high (typically pulled to VREF/VCC). If ≈0 V, trace back to the protection/MCU/thermal/DC‑detect that’s pulling it low; do not force it high until the cause is found.
  • FAULT: should be high (via pull‑up). If low, you’re in protection—inspect OCSET network and the power stage for shorts or abnormal current paths. 3) If VCC and VREF OK, CSD high, FAULT high, but still no switching:
  • Probe IN+/IN− for realistic mid‑bias and small‑signal activity from the self‑osc loop.
  • Check DT/OCSET resistor values against the BOM; replace suspect SMDs proactively.
  • Verify bootstrap diode (forward drop ≈0.2–0.6 V depending on type) and Cboot ESR/capacitance; replace aged electrolytics/local ceramics near the driver. 4) Isolate to protect the new IC: Lift/remove gate resistors to the MOSFETs, power only VCC to the IRS20957, confirm VREF and logic behavior (CSD/FAULT). Then reintroduce the low‑voltage/higher rails and reconnect gates after logic looks correct.
• Oscilloscope checkpoints (after shorts are ruled out)
  • LO: clean pulses 0↔VCC referenced to COM at tens to hundreds of kHz when running.
  • VB–VS: ≈VCC once the first LO conduction occurs; ripple indicates normal bootstrap charging.
  • VS: switching node should toggle between the rails with appropriate dead time; any stuck level indicates half‑bridge/device fault or persistent shutdown.
• Parts/handling best practices
  • Use genuine IRS20957S from authorized distributors; clean flux and inspect under magnification to avoid leakage paths.
  • Replace MOSFETs in complementary pairs and always verify gate resistors and snubbers; a bad snubber or open gate resistor will instantly re‑destroy a fresh driver.

Possible disclaimers or additional notes

• Exact test points and pin numbering vary by board revision; always verify against the IRS20957S datasheet and the KW153 PCB silkscreen/layout. Some modules also introduce MCU‑controlled sequencing that can hold CSD low until all rails and thermal sensors read OK.

Suggestions for further research

• Review the IRS20957/IRS20957S datasheet sections on UVLO, CSD timing/reset, FAULT behavior, OCSET programming, and recommended bootstrap networks.
• Study self‑oscillating Class‑D loop application notes (startup biasing, IN+/IN− conditioning) to understand non‑start edge cases.
• If available, consult the KW‑series service literature for rail sequencing and protection logic, especially how the module’s supervisor drives CSD.

Brief summary

• In a KW153, “IRS20957 not starting” with both HO/LO low almost always traces to UVLO, CSD held low, or FAULT (often from OCP) rather than a “missing PWM.” Prove VCC and VREF first, then CSD and FAULT logic, then the bootstrap path and self‑osc feedback network, and finally the power stage devices and OCSET parts. Replace any shorted MOSFETs/failed passives before fitting a new, genuine IRS20957S, and only reintroduce full rails after confirming the driver’s low‑voltage behavior is sane.

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