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Nie, dziękuję Przekieruj mnie tamProASIC3 free library
• The complete, vendor-supported “free library” for any ProASIC3 device is delivered with Microchip’s Libero SoC Design Suite (Silver/Gold licence tiers cost $0).
• Libero installs:
– Synthesis & simulation primitive libraries (the IGLOO/ProASIC3 Macro Library).
– A catalogue of no-fee IP (“DirectCores”: CoreUART, CoreSPI, CoreGPIO, etc.).
– Pre-compiled simulation models for ModelSim-ME, Riviera-PRO, VCS.
• For PCB work, free schematic symbols / footprints are available from Ultra Librarian, SnapEDA, SamacSys.
• Community/open-source VHDL/Verilog cores (OpenCores, GitHub, Hackaday) can be mixed in, but Microchip libraries remain the reference for device-specific elements.
What “library” means in a ProASIC3 context
• Primitive / macro library – gate-level building blocks (DFF, INBUF, CCC, RAM4K18, …).
• IP cores – synthesizable, verified blocks (UART, SPI, FIFO, timers, etc.).
• Simulation libraries – timing netlists + SDF for post-layout verification.
• PCB CAD libraries – schematic symbols, BGA/TQFP footprints.
Vendor resources (always the safest starting point)
a. Libero SoC Design Suite
– Current release 2023.2 (Apr-2024) supports Windows 10/11 & RHEL 8/9.
– Licence tiers: Silver (free, device-size-limited), Gold (free for flash FPGAs up to 250 k gates), Platinum (paid).
– During installation Libero drops all required libraries into
..\Microchip\Libero\designer\lib\{verilog|vhdl}\proasic3.
– The same installer includes ModelSim-ME 2021.3 with pre-compiled proasic3_ver / proasic3_vhdl libraries.
b. IGLOO / ProASIC3 / SmartFusion Macro Library Guide
– PDF links (Rev 4.5, Feb-2024):
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/pa3_libguide_ug.pdf
– Contains: instantiation templates, truth tables, timing arcs, resource usage.
| c. Free DirectCores (selected) | Core name | Function | Free w/ Silver? | Notes |
|---|---|---|---|---|
| CoreUART | 8-bit UART, up to 1 Mbaud | ✔ | SmartGen configurable | |
| CoreI2C | I²C master/slave | ✔ | Supports multi-master | |
| CoreSPI | SPI master/slave | ✔ | 8-bit to 32-bit frames | |
| CoreTimer | 32-bit misc timer | ✔ | Interrupt capable | |
| CoreGPIO | Debounced I/O block | ✔ | Up to 32 lines | |
| CoreFIFO | On-chip FIFO w/handshakes | ✔ | Uses RAM4K18 |
Open-source / community options
• OpenCores.org – processors (OpenRISC, 8051), Ethernet MACs, AES, etc.
• Hackaday project “VHDL Library for Gate-Level Verification” – AGPLv3, useful when proprietary simulators are unavailable.
• GitHub keyword search “proasic3” shows ready-to-run examples (RISC-V on A3P250, video-out demos).
Caution: these cores are generic; only vendor libs know about CCC, FlashROM, FROM, ESD circuits, etc.
Practical integration flow (Libero 2023.x example)
1) Install Libero SoC → request a free Gold licence (good for A3P030-A3P1000).
2) Start a project, choose your device (e.g. A3P250-FGG256).
3) For IP: Tools → IP Catalog → right-click “CoreUART” → “Configure & Generate”. Libero places generated HDL plus an .xcix descriptor into /component/work/.
4) Simulation: Libero’s “Run Simulation” button calls ModelSim with the correct vsim -L proasic3_ver flags; for external ModelSim add vmap proasic3_ver $LIBERO/…/proasic3_ver.
5) PCB: Download symbol/footprint from Ultra Librarian, verify pitch, via stub length, clearance per IPC-7351B, and cross-check pin-mapping with DS0128 datasheet.
Device-specific quirks
• ProASIC3 is flash-based; no configuration bit-stream SEU, but antifuse routing for CCC nets.
• CCC macro has PLL but only ÷ / × integer ratios; confirm jitter with SmartTime PVT sweep.
• RAM4K18 is single-port or true dual-port; use CoreFIFO to auto-generate wrapper with gray-coded pointers.
• Microchip gradually EOLs legacy antifuse families; ProASIC3 still on long-term supply schedule (2035 +).
• New Libero revisions focus on security (bitstream encryption, sNVM), but Flash-based “prototyping once, deploy forever” remains the selling point.
• Community is porting small RISC-V cores (e.g., SERV) that fit in A3P60 (<8 k gates).
• Timing models: post-layout SDF is generated by Designer-24.1. Import the SDF into ModelSim:
vsim -sdftyp /tb/dut=impl1.sdf work.tb(glbl)
• Primitive instantiation example – crystal oscillator buffer:
OSCILLATOR #( .HFOSCEN(1) ) u_osc ( .OSC(osc_raw) );
CLKINT u_clkbuf ( .A(osc_raw), .Y(clk_sys) );• Analogy: think of Libero libraries as the “standard library” for C – you can write printf yourself, but vendor code already solves corner-cases (IOB slew, DRC).
• Vendor primitive & IP libraries are under Microchip EULA: free to use in designs targeting Microchip FPGAs, redistribution prohibited.
• Open-source cores: respect licence (GPL/AGPL vs permissive). Mixing GPL cores with proprietary IP may impose reciprocal requirements.
• Export controls: certain encryption-capable IP (CoreAES, CoreDES) subject to US ECCN 5A002.
• Always lock a Libero/ModelSim version per project to ensure simulation-to-silicon correlation.
• Run SmartTime → Timing Verification for worst-case −40 °C, 1.425 V (core), 1.89 V (IO 1.8 V), 90 % activity factor.
• Use SmartPower to estimate flash-cell write current if in-system program/erase is planned.
• For PCB footprints, inspect BGA escape patterns – ProASIC3’s “×” rows have no balls, enabling two-layer escape for ≤A3P250-FGG256.
• Some complex IP (DDR, Cortex-M1) is not free; only evaluation netlists are accessible under Silver/Gold.
• Latest Libero drops Windows 7 support; keep a frozen install if maintaining legacy products.
• Open-source simulation libs do not cover flash-specific behaviour (erase/write cycles).
• Investigate using ProASIC3L (low-leakage variant) for battery-powered designs.
• Evaluate SERV or PicoRV-based soft-cores plus CoreSPI for fully open RISC-V platform.
• Explore Microchip’s new embedded‐flash FPGA family (PolarFire SoC) if you require hardened RISC-V + Linux.
The only “official” free library for ProASIC3 is installed automatically with Microchip’s Libero SoC (Silver/Gold). It supplies primitive macros, pre-compiled simulation models, and a catalogue of no-charge IP cores. Supplement this with community VHDL/Verilog from OpenCores or GitHub and free PCB footprints from Ultra Librarian. Begin by downloading Libero SoC 2023.x, requesting a free licence, and consulting the IGLOO/ProASIC3 Macro Library Guide for instantiation templates and timing data.