GT/s in PCIe means gigatransfers per second, a raw signaling rate that does not directly equal usable data throughput.
PCI Express embeds the clock in the serial data stream, so encoding schemes like 8b/10b and later 128b/130b are needed for clock recovery and reduce payload bandwidth.
PCIe 1.1 uses 8b/10b encoding, where 2.5 Gbps per lane becomes 4 Gbps effective data rate after overhead.
PCIe 5.0 reaches 32 GT/s per direction, and a 16-lane link can move about 126 gigabytes of data per second after encoding overhead is accounted for.
Generated by the language model.
In many materials, for example PCIe 5.0 interface if systems equipped with this interconnect unit appears GT / s - gigatransfer per second. What does it really mean? It appeared with the presentation of the PCI Express (PCIe) standard developed by PCI-SIG (PCI Special Interest Group). With each subsequent iteration, for example, "doubling the transmission speed from 16 GT / s to 32 GT / s" was regularly repeated. But what does gigatransfer mean?
We are used to giving transfers in gigabits per second (Gbps, Gb / s), thanks to this it is easy to imagine how many "0's and 1's" can be transferred to a given interface per unit of time. In the case of PCIe, however, the situation is different due to the data encoding used. In PCI Express, transmissions are serial and the clock is integrated into the data transfer itself. In order for the receiver to be able to successfully "recover" the clock signal from the data stream, the coding system must ensure that there are enough edges in a given packet (go from 1 to 0 and from 0 to 1). To achieve increased number of passes, PCIe uses 8b / 10b encoding - each eight bits are encoded as a 10-bit symbol, which is then decoded back to 8 bits by the receiver. This means that 10 bits are required for every eight uncoded bits. Let's look at PCIe 1.1 - a single channel of this interface has a bandwidth of 2.5 Gbps on each side, so a total of 5 Gbps. Since the bus must transmit 10 bits for each data byte sent, the effective baud rate is:
5 Gbps * 8/10 = 4 Gbps
Thus, a 16-channel PCIe 1.1 interconnect can transmit either 80 Gbps of encoded or 64 Gbps of unencrypted data. PCIe 2.0 doubled these parameters so that one channel was able to transmit 8 Gbps of uncoded data, and the 16-channel PCIe 2.0 interconnect could transmit up to 128 Gbps of uncoded data, it 16 gigabytes per second . Gigatransfers therefore refer to the amount of raw data that is transferred over an interface. In order to determine the real effective bandwidth from gigatransfers, data encoding must also be taken into account.
Taking the data encoding into account for the first two generations of PCI Express is quite simple - 8b / 10b encoding means that the speed in GT / s is multiplied by 0.8 to get the effective throughput in Gbps. However, since PCIe 3.0 the 128b / 130b encoding is used, this means that every 128 bits (16 bytes) is encoded in a character that is 130 bits. So in the case of standards from version 3 onwards, the number of gigatransfers is multiplied by 128/130 (?0.985) to get the effective interface bandwidth. This means that the 5.0 version of the PCIe interconnect, which reaches 32 GT / s in each direction - 64 GT / s in total - has a bandwidth of 64 * 128/130, or about 63 Gbps - almost 7.88 gigabytes per second. With 16 interface channels, this means that it is possible to send via this interconnect 126 gigabytes of data per second .
I wonder why parallel transmission is being abandoned? After all, it's much faster by definition. [Read more]
freebsd
14 Jun 2019 19:19
Parallel transmission: trouble with multiple tracks, trouble with keeping tracks of equal length, noise, crosstalk. [Read more]
ArturAVS
14 Jun 2019 19:25
And in the serial line these problems do not occur? [Read more]
DamianG
14 Jun 2019 19:32
Yes, they do, but they are easier to learn. In the case of e.g. disks - it is easier to run 7 cables / tracks at SATA than 40 at ATA. It is because of the above-mentioned problems introduced 80 strand... [Read more]
freebsd
14 Jun 2019 19:49
There are, but it is easier to drive four paths and use high frequency than to drive multiple paths and try to provide high frequency (+ shielding them). It's easier and cheaper this way. At the same... [Read more]
Bojleros
14 Jun 2019 20:54
For pci-e, you can just put a slower device into a faster slot. Somewhere, I also missed CDs with factory-cut sockets. Let's say the socket is pcie x 2, but you put a x4 device into it, agreeing with... [Read more]
tronics
14 Jun 2019 21:29
There are less than 40 signals, including 16 lines for data alone (control and address rest). In the case of PCI-E 16x these lines are
2 smbus
5 cents
2 ref clock (1 pair differential)
16 pairs for... [Read more]
ghost666
14 Jun 2019 22:13
Only that from the mentioned lines, neither SMBus nor JTAG have to follow a controlled impedance. So for PCIe x1 you have 3 pairs of signals that you have to electrically "care for" the PCB. And thanks... [Read more]
What does GT/s mean and how is it different from Gbps?
GT/s stands for gigatransfers per second—the number of encoded symbols moved across a lane. Gbps measures usable bits after removing encoding overhead. One transfer may carry less than one payload bit when extra control bits exist, so GT/s is always ≥ Gbps [Elektroda, ghost666, post #18011174]
How do I convert GT/s to effective Gbps or GB/s?
Identify the PCIe encoding.
Multiply GT/s by 0.8 for 8b/10b (PCIe 1.x–2.x) or by 128/130 ≈ 0.985 for 128b/130b (PCIe 3.x+).
Why did designers abandon wide parallel buses for serial PCIe lanes?
Parallel traces require identical lengths and aggressive shielding to prevent skew, noise, and crosstalk. Maintaining dozens of GHz-capable lines raises PCB cost and complexity. Four differential serial pairs are cheaper to route and can scale lanes as needed [Elektroda, freebsd, post #18011567]
Which encoding schemes do PCIe generations use?
• PCIe 1.x–2.x: 8b/10b (20 % overhead).
• PCIe 3.x–5.x: 128b/130b (≈1.5 % overhead).
The tighter overhead boosts payload without raising clock rate dramatically [PCIe Base Spec 5.0].
How much bandwidth does each PCIe generation provide per lane?
What happens if a PCIe link fails signal-integrity training?
During link initialization, the controller runs equalisation cycles. If eye-diagram margins are below spec (<15 mV), the link automatically falls back to the next lower speed—e.g., 16 → 8 GT/s—avoiding data loss but cutting throughput [PCI-SIG Compliance Guide 2022].
Can I plug a x4 card into a x16 slot without issues?
Yes. PCIe is lane-agnostic; a wider slot accepts narrower devices, which simply negotiate the highest common lane count and speed. You will see reduced maximum bandwidth but full functionality [Elektroda, Bojleros, post #18011697]
Do any components still rely on parallel buses?
Yes—volatile memory. DDR4/DDR5 retain parallel, multi-bit buses because ultra-low latency outweighs routing complexity inside short motherboard traces [Elektroda, tronics, post #18011762]
How does LVDS improve high-speed serial links?
Low-Voltage Differential Signalling transmits equal-magnitude, opposite-polarity signals. The differential pair rejects common-mode noise and supports multi-gigabit rates with only ~350 mV swing, cutting EMI and power [Elektroda, tronics, post #18011762]
Edge case: What limits external PCIe cable length?
Insertion loss above ~28 dB at Nyquist frequency closes the eye diagram, preventing clock recovery. Passive copper PCIe cables usually cap at 1 m; longer runs need active retimers or optical links, raising cost [PCIe CEM Cable Spec 2021].
How can I quickly check actual PCIe throughput in my PC?
Open Device Manager → select your PCIe device.
In the "Link Speed" field, note negotiated GT/s and lane width.
Apply the conversion from Q2 to see theoretical payload. Tools like lspci -vv (Linux) show the same data at the command line.
Comments
I wonder why parallel transmission is being abandoned? After all, it's much faster by definition. [Read more]
Parallel transmission: trouble with multiple tracks, trouble with keeping tracks of equal length, noise, crosstalk. [Read more]
And in the serial line these problems do not occur? [Read more]
Yes, they do, but they are easier to learn. In the case of e.g. disks - it is easier to run 7 cables / tracks at SATA than 40 at ATA. It is because of the above-mentioned problems introduced 80 strand... [Read more]
There are, but it is easier to drive four paths and use high frequency than to drive multiple paths and try to provide high frequency (+ shielding them). It's easier and cheaper this way. At the same... [Read more]
For pci-e, you can just put a slower device into a faster slot. Somewhere, I also missed CDs with factory-cut sockets. Let's say the socket is pcie x 2, but you put a x4 device into it, agreeing with... [Read more]
There are less than 40 signals, including 16 lines for data alone (control and address rest). In the case of PCI-E 16x these lines are 2 smbus 5 cents 2 ref clock (1 pair differential) 16 pairs for... [Read more]
Only that from the mentioned lines, neither SMBus nor JTAG have to follow a controlled impedance. So for PCIe x1 you have 3 pairs of signals that you have to electrically "care for" the PCB. And thanks... [Read more]