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• Parallel connection → capacitances add; voltage the same on every capacitor; increases total capacitance and ripple-current capability.
• Series connection → reciprocals add; charge identical in every capacitor; voltage divides; lowers equivalent capacitance but raises the permissible overall working voltage.
Key uses: parallel for bulk energy storage / low-ESR filtering; series for high-voltage stacks, capacitive dividers, or creating small precise values.
Electrical relationships
a) Parallel
• \(C\text{eq}= \sum{k=1}^{n}C_k\)
• \(V_1=V2=\dots =V\text{in}\)
• \(Q\text{tot}=C\text{eq}V\) and \(I\) splits according to \(I_k=C_k\,dV/dt\).
• ESR and ESL are paralleled, so both drop roughly in proportion to the number of parts, improving high-frequency performance.
b) Series
• \(\displaystyle\frac{1}{C\text{eq}}=\sum{k=1}^{n}\frac{1}{Ck}\) → \(C\text{eq}<\min(C_k)\)
• Charge is common: \(Q_1=Q2=\dots=Q\text{line}\)
• \(V_\text{tot}= \sum V_k = Q \sum \frac{1}{C_k}\) (voltage divides inversely with \(C_k\)).
• Equivalent ESR = sum of individual ESRs; ESL likewise, so high-frequency impedance rises.
Physical interpretation (parallel-plate model)
• Parallel → effective plate area increases ⇒ higher \(C\).
• Series → effective dielectric thickness increases ⇒ lower \(C\) but greater breakdown distance ⇒ higher voltage withstand.
Energy
• Stored energy \(E=\tfrac12 C\text{eq}V\text{tot}^2\).
• For the same supply voltage, parallel stores more energy; series stores less but tolerates higher \(V_\text{tot}\).
Non-idealities
• Leakage current variance causes unequal voltage sharing in series stacks; add “balancing” resistors (≈0.1–1 MΩ) or active balancers for DC.
• Tolerance mismatch in parallel causes unequal current spikes during transients; keep similar types, lengths, and layout.
Frequency domain
• Parallel lowers impedance at switching frequencies (decoupling).
• Series increases impedance but can form intentional series-resonant networks (e.g., snubbers, AC coupling).
• Multi-layer ceramic capacitor (MLCC) arrays: OEMs now ship 0201 and 01005 MLCCs pre-paralleled on a single package to reduce ESL further—common on 5 G and DDR5 boards.
• Series-stacked film or polypropylene capacitors dominate EV traction inverters at 800–1000 V; automatic active-balancer ICs (e.g., Texas Instruments LM74670-Q1, ST STCMB1) are becoming standard.
• Supercapacitor banks for UPS and regenerative braking: cells (2.7 V each) routinely run 18–24 in series, with digital cell-balancing modules to combat rapid self-leakage changes over life.
Analogy: Water tanks
• Parallel tanks side-by-side (wide base) give more water at the same height (pressure).
• Series tanks stacked vertically give the same volume flow but higher pressure rating.
Example calculation
Given two 47 µF, 25 V electrolytics:
• Parallel ⇒ 94 µF, 25 V.
• Series ⇒ \(C_\text{eq}= (47·47)/(47+47)=23.5 µF\); voltage rating ≈ 50 V (use 40 % derating ⇒ 20 V / 40 V respectively).
• Safety: Exceeding working voltage in series stacks risks dielectric punch-through and fire. Follow IEC 60384, UL 810, and automotive AEC-Q200 derating tables.
• Environmental: Large electrolytic banks contain solvents (e.g., GBL); WEEE & RoHS restrict certain electrolytes and Pb-based solders. Proper recycling is mandated.
• Privacy/security: In tamper-evident designs, discharging high-value energy-storage capacitors before servicing prevents lethal shock. IEC 60950/62368 enforce <60 V within 2 s.
• Always match capacitance, voltage rating, ESR, temperature coefficient in series strings.
• Add 1 %–2 % tolerance, 0.5–1 MΩ resistors across each device for DC balance ≥100 V.
• Derate voltage: electrolytics 20–30 %, ceramics 10 – 15 %, film 5 – 10 %.
• Layout: keep leads short; in parallel, place physically close to reduce inductive loops.
• Test: measure voltage share with HV probes, perform thermal imaging for hot-spot ESR.
Potential challenges & fixes
• Unequal leakage → thermal runaway; solution: active balancer ICs.
• EMI from large current loops in paralleled caps; use ground planes and staggered values (bulk + X7R + NP0).
• Capacitance of high-κ MLCCs derates with DC bias; stacking in parallel may not linearly scale—check manufacturer bias curves.
• Polarized electrolytics in AC require back-to-back connection or non-polar types.
• Voltage division in series under fast transients can overshoot ratings even with DC balance; consider RC snubbers.
• Graphene and conductive-polymer super-capacitors for >10 Wh/kg storage.
• Integrated digital balancing for series stacks (research at Univ. of Arkansas, 2023).
• Wide-bandgap (GaN/SiC) converters pushing switching nodes >800 V—impact on required film-cap series stacks.
Resources:
– Kemet “Guide to Stacking MLCCs,” 2022.
– IEEE Transactions on Power Electronics, Special Issue on Capacitor Technologies, April 2023.
– Texas Instruments application note “Active Balancing for Supercapacitor Banks,” 2024.
Parallel capacitors raise total capacitance, share identical voltage, and lower ESR—ideal for energy storage and decoupling. Series capacitors lower capacitance but let you withstand higher voltages or fine-tune small values; they carry identical charge and require voltage-balancing measures to remain safe. Modern designs increasingly use large parallel MLCC arrays for high-speed decoupling and controlled series stacks (with active balancers) for high-voltage energy buffers, all governed by strict safety and environmental standards.
