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Coplanar waveguide impedance is the characteristic impedance \(Z_0\) of a transmission line made from a center signal conductor with ground conductors on the same plane, separated by narrow gaps.
For a basic symmetric coplanar waveguide:
\[ Z0=\frac{30\pi}{\sqrt{\varepsilon\text{eff}}}\frac{K(k')}{K(k)} \]
where:
\[ k=\frac{W}{W+2G} \]
\[ k'=\sqrt{1-k^2} \]
In practical PCB design, the impedance is usually calculated using a field solver, PCB impedance calculator, or RF/microwave CAD tool rather than by hand.
A coplanar waveguide, usually abbreviated CPW, is a planar RF transmission line. Its basic structure is:
Ground Gap Signal trace Gap Ground
========= G ============ G =========
W
----------------------------------------------------
dielectric substrateUnlike a microstrip, where the return plane is below the trace, a CPW places the signal trace and the ground conductors on the same copper layer.
The impedance is not simply resistance. It is the transmission-line characteristic impedance:
\[ Z_0=\sqrt{\frac{L'}{C'}} \]
where:
For a low-loss line, this also relates to propagation velocity:
\[ Z_0=\frac{1}{v_p C'} \]
with:
\[ vp=\frac{c}{\sqrt{\varepsilon\text{eff}}} \]
So CPW impedance depends primarily on how much capacitance exists between the center trace and the two ground conductors, and how much of the electric field is in air versus dielectric material.
The main parameters are:
| Symbol | Meaning | Effect on impedance |
|---|---|---|
| \(W\) | Center conductor width | Larger \(W\) lowers \(Z_0\) |
| \(G\) or \(S\) | Gap between signal and ground | Larger gap raises \(Z_0\) |
| \(h\) | Substrate thickness | Affects field distribution |
| \(t\) | Copper thickness | Important for accurate PCB work |
| \(\varepsilon_r\) | Substrate relative permittivity | Higher \(\varepsilon_r\) lowers \(Z_0\) |
| solder mask | Dielectric coating over line | Usually lowers \(Z_0\) |
The most important first-order geometry ratio is:
\[ k=\frac{W}{W+2G} \]
This expresses how wide the center trace is relative to the total signal-plus-gap region.
For an ideal, symmetric, ungrounded CPW with infinitely wide ground planes and negligible conductor thickness, the impedance is commonly calculated using conformal mapping.
Define:
\[ k=\frac{W}{W+2G} \]
\[ k'=\sqrt{1-k^2} \]
The complete elliptic integral of the first kind is:
\[ K(k)=\int_0^{\pi/2}\frac{d\theta}{\sqrt{1-k^2\sin^2\theta}} \]
Then the characteristic impedance is:
\[ Z0=\frac{30\pi}{\sqrt{\varepsilon\text{eff}}}\frac{K(k')}{K(k)} \]
where \(30\pi \approx 94.25\ \Omega\).
For a very thick dielectric substrate with air above the line, a common approximation is:
\[ \varepsilon_\text{eff}\approx\frac{\varepsilon_r+1}{2} \]
because part of the field is in air and part is in the dielectric.
The effective dielectric constant \(\varepsilon_\text{eff}\) is not usually equal to the substrate dielectric constant \(\varepsilon_r\). Since the CPW fields exist partly in air and partly inside the substrate:
\[ 1 < \varepsilon_\text{eff} < \varepsilon_r \]
A useful physical interpretation is:
\[ \varepsilon\text{eff}=\frac{C\text{with dielectric}}{C_\text{with air only}} \]
For finite substrate thickness, a more accurate expression uses another elliptic-integral modulus.
Let:
\[ a=\frac{W}{2} \]
\[ b=\frac{W}{2}+G \]
\[ k=\frac{a}{b}=\frac{W}{W+2G} \]
For finite substrate thickness \(h\):
\[ k_1= \frac{ \sinh\left(\frac{\pi a}{2h}\right) }{ \sinh\left(\frac{\pi b}{2h}\right) } \]
\[ k_1'=\sqrt{1-k_1^2} \]
A commonly used conformal-mapping approximation is:
1+ \frac{\varepsilon_r-1}{2} \frac{K(k')}{K(k)} \frac{K(k_1)}{K(k_1')} \]
Then that \(\varepsilon_\text{eff}\) is substituted into:
\[ Z0=\frac{30\pi}{\sqrt{\varepsilon\text{eff}}}\frac{K(k')}{K(k)} \]
This is the classical analytical basis for CPW impedance calculation.
In PCB design, a very common variant is grounded coplanar waveguide, also called:
This structure has the same top-layer CPW geometry, but also includes a solid ground plane under the substrate:
Top layer:
Ground Gap Signal trace Gap Ground
========= G ============ G =========
Dielectric substrate, thickness h
Bottom layer:
================ solid ground plane ================This bottom ground plane increases capacitance and usually lowers impedance compared with an unbacked CPW of the same \(W\), \(G\), and dielectric material.
The calculation is more complex because the field terminates both on the coplanar grounds and on the lower ground plane. Analytical models introduce additional elliptic-integral terms, commonly involving:
\[ k_2= \frac{ \tanh\left(\frac{\pi a}{2h}\right) }{ \tanh\left(\frac{\pi b}{2h}\right) } \]
\[ k_2'=\sqrt{1-k_2^2} \]
A simplified form for conductor-backed CPW often has the structure:
\[ Z0 \propto \frac{1}{\sqrt{\varepsilon\text{eff}}} \frac{1}{ \frac{K(k)}{K(k')}+ \frac{K(k_2)}{K(k_2')} } \]
The exact expression depends on the model assumptions, such as finite ground width, conductor thickness, solder mask, and dielectric layering. For that reason, CPWG is usually calculated using a 2D field solver or PCB impedance tool.
For a fixed substrate and copper thickness:
| Change | Effect on CPW impedance |
|---|---|
| Increase center trace width \(W\) | Decreases \(Z_0\) |
| Decrease center trace width \(W\) | Increases \(Z_0\) |
| Increase gap \(G\) | Increases \(Z_0\) |
| Decrease gap \(G\) | Decreases \(Z_0\) |
| Increase dielectric constant \(\varepsilon_r\) | Decreases \(Z_0\) |
| Add solder mask | Usually decreases \(Z_0\) |
| Add bottom ground plane | Usually decreases \(Z_0\) |
| Move bottom ground plane closer | Decreases \(Z_0\) for CPWG |
A useful mental model is that impedance is inversely related to capacitance:
\[ Z_0 \sim \frac{1}{C'} \]
A wider trace, smaller gap, higher dielectric constant, or closer ground plane increases capacitance, so impedance falls.
Suppose you want a 50-ohm CPW or CPWG line.
You would normally proceed as follows:
Define the PCB stackup:
Choose a manufacturable gap \(G\), for example:
Adjust the trace width \(W\) until the calculated impedance reaches 50 ohms.
Verify using:
For RF and microwave PCB work, especially above a few GHz, relying only on the closed-form formula can be risky because real geometry matters.
The ideal formula assumes perfect rectangular conductors, infinite ground planes, and homogeneous dielectric. Real boards are not ideal.
Important practical corrections include:
The simple formula assumes zero-thickness metal. Real copper has finite thickness, which changes the effective gap and capacitance.
Thicker copper generally lowers impedance slightly.
PCB traces are often trapezoidal rather than rectangular due to etching. This affects both \(W\) and \(G\), especially for narrow RF gaps.
Solder mask has a dielectric constant typically around 3 to 4. If it covers the CPW gaps, it increases capacitance and lowers impedance.
For precision RF lines, designers often remove solder mask over CPW structures.
The analytical formula assumes laterally infinite ground planes. If the coplanar ground pours are too narrow, the impedance changes and radiation can increase.
For CPWG, the top ground pours should be tied to the bottom ground plane using via stitching. Poor via placement can cause unwanted slotline modes.
As a rule of thumb, via spacing should be much less than the wavelength at the highest operating frequency, and should usually be placed close to the CPW gaps without violating manufacturing clearance.
The impedance formula gives the lossless or quasi-static characteristic impedance. At high frequency, additional effects matter:
For engineering design:
Use closed-form equations for first estimates.
They are useful for understanding trends and approximate dimensions.
Use a 2D field solver for PCB production values.
This accounts for copper thickness, solder mask, dielectric stackup, and etch geometry.
Use a 3D EM solver for transitions and discontinuities.
CPW launches, connectors, bends, pads, filters, antennas, and via transitions need 3D simulation at microwave and millimeter-wave frequencies.
Ask the PCB fabricator for controlled-impedance rules.
The actual manufactured impedance depends on their laminate, copper plating, etch compensation, and process tolerances.
Measure critical designs.
Use TDR for impedance profile or a VNA for S-parameters.
Coplanar waveguide impedance is the characteristic impedance of a planar transmission line where the signal trace and ground conductors are on the same layer. It is mainly determined by trace width \(W\), gap \(G\), substrate permittivity \(\varepsilon_r\), substrate thickness \(h\), and copper thickness \(t\).
For an ideal symmetric CPW:
\[ Z0=\frac{30\pi}{\sqrt{\varepsilon\text{eff}}}\frac{K(k')}{K(k)} \]
with:
\[ k=\frac{W}{W+2G} \]
\[ k'=\sqrt{1-k^2} \]
In real PCB design, especially for grounded CPW, the formula becomes more complex, so impedance is usually calculated with a PCB impedance calculator, 2D field solver, or full-wave EM simulation.