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Product genealogy and OEM variants
• VS-550 “V1/V2” (≈2013-2017, HEC): group-regulated forward converter, no DC-to-DC modules, passive PFC.
• VS-550 “V3” (≈2018-2020, CWT GPA platform): active boost PFC, double-forward topology, group regulation.
• VS-550 “V4” / current retail part-number CP-9020171-xx (CWT GPB platform): active PFC + synchronous rectification on +12 V, DC-to-DC daughter-cards for +5 V / +3.3 V.
Different revisions use different controller ICs, so always identify the PCB code silkscreen and IC part numbers before assuming a circuit.
Typical functional blocks (current GPB revision, 80 PLUS White)
Primary (HOT side)
• EMI/RF filter → fuse → NTC inrush limiter
• Bridge rectifier (GBU808 or similar)
• Active PFC boost stage
– Controller: Champion CM6500 or OnSemi NCP1653D
– MOSFET: 600 V Super-Junction (e.g., IPA60R190P6)
• PFC boost diode & 450 V bulk capacitor (~2 × 220 µF)
• Main power stage: double-forward (or half-bridge forward in older boards)
– PWM combo controller: SG6105D / CM6802
– 2 × MOSFETs on primary heatsink
• 5 V SB flyback supply
– PI TNY278 / TNY280 or Silergy SY50289 (8-pin)
Secondary (COLD side)
• +12 V synchronous rectification
– Vishay SiRA12 or Alpha-Omega AOZ2081 driver
• +5 V / +3.3 V DC-to-DC buck converters (each on a vertical daughterboard)
– Controller: APW7159, Anpec APW7073 or equivalent
• Supervisor IC
– Weltrend WT7527, Sitronix PS223 or GR8323: OVP/UVP/OCP/SCP, POWER-GOOD timing
• Common LC filters and differential chokes per rail
Protection thresholds (typical WT7527) | Rail | UVP | OVP | OCP (per rail) |
---|---|---|---|---|
+12 V | 10.4 V | 13.4 V | 45–55 A | |
+5 V | 4.3 V | 5.8 V | 25–35 A | |
+3.3 V | 2.9 V | 3.9 V | 22–30 A |
Reverse-engineering approach without an official schematic
a. Identify ICs and download their datasheets – each comes with an “application circuit” that is 80 – 90 % identical to what is on the VS-550.
b. Mark functional blocks on photos of the PCB; trace high-current paths with a continuity buzzer.
c. Draw a block diagram first, then add component identifiers only where measurement is required.
d. Verify static parameters before energising:
– Bridge diode drop, MOSFET D-S short, bulk-cap ESR, PFC diode reverse leakage.
e. Power-up sequence checks (with an isolation transformer & bulb limiter):
Common field failures
• Dried 5 V SB VCC electrolytic (4.7 – 10 µF, 50 V) → standby hic-cup.
• Shorted synchronous-rect MOSFET on +12 V → blown secondary fuse-link, OCP trip.
• Open PFC start-up resistor (2 × 270 kΩ) → no PFC, low bulk voltage, PSU only runs on 115 V mains.
• Bad output caps (CapXon / Teapo SC series) → ripple > 120 mV_pp, system instability.
Why no public schematic?
Analogy: Treat the datasheet “typical application” as the sub-assemblies; your job is only to draw the inter-wiring between those blocks on your specific board.
No official Corsair schematic for the VS-550 exists publicly. The unit’s design depends on revision: early versions are group-regulated forward, the latest GPB revision adds active PFC, synchronous rectification and DC-to-DC modules. For repair, locate the PCB revision, download all controller datasheets and rebuild a block-level diagram; that, plus safe bench techniques, provides everything necessary to diagnose or refurbish the PSU without violating Corsair’s intellectual-property policies.