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A non-inverting op-amp amplifies the input without flipping its polarity, with a precise closed-loop gain of \(A_v = 1+\dfrac{R_f}{R_1}\) and a typical input impedance that can exceed 10 TΩ in modern CMOS devices [1] – a combination that makes it the default choice whenever you need high-impedance buffering or phase-preserving gain.
Operating principle
• Input \(V_{IN}\) is applied to the + node; the − node is driven by a feedback divider \(R_1!-!Rf\).
• The op-amp’s large open-loop gain forces the differential input voltage toward zero (“virtual short”), so \(V-≈V+≈V{IN}\).
• Solving the divider equation gives
\[
V{IN} = V{OUT}\frac{R_1}{R_1+R_f}\;\Longrightarrow\;
Av=\frac{V{OUT}}{V_{IN}} = 1+\frac{R_f}{R_1}.
\]
• Phase shift = 0 °, hence “non-inverting” [2].
| Key quantitative facts (Statistics Addition) | Parameter (typ.) | Value | Comment | Source |
|---|---|---|---|---|
| Input impedance | 1 MΩ – 10 TΩ | CMOS zero-drift op-amps such as OPA388 | [3] | |
| Closed-loop BW | \( \text{GBW}/A_v \) | e.g., 10 MHz GBW → 1 MHz at \(A_v=10\) | [4] | |
| Slew rate | 0.5 V/µs – 20 V/µs | Limits large-signal HF response | [4] | |
| Offset voltage | < 1 µV (auto-zero) to 5 mV (general-purpose) | Amplified by \(A_v\) | [3] |
“A non-inverting amplifier is often chosen because it ‘offers extremely high input impedance while maintaining a predictable, resistor-set gain’” — Texas Instruments, Op-Amps for Everyone (Quote Addition) [5].
• Rail-to-rail, zero-drift CMOS op-amps (e.g., ADI ADA4522) push input impedance into the tera-ohm range while keeping offset below 5 µV, enabling direct amplification of pH probes and MEMS sensors [3].
• Automotive and IoT designs frequently use single-supply 3.3 V, so R1 is tied to a mid-supply bias instead of ground to keep the common-mode voltage in range [6].
• Unity-gain stability is no longer universal; high-speed parts like THS3491 require \(A_v≥5\) to avoid phase-margin collapse [7].
Resistor selection
– Keep 1 kΩ ≤ R1 ≤ 100 kΩ to balance noise, loading, and bias-current error.
– Match the dc resistance seen by both inputs: add \(R_{COMP}=R_1\parallel R_f\) in series with the + input if the source impedance is < 1 kΩ to cancel bias-current–induced offset [5].
PCB layout
– Place \(R_f\) as close as possible to the op-amp pins; route the feedback trace over a ground plane to minimize loop area and parasitic C.
– Bypass each supply pin with 100 nF (X7R) + 1 µF (bulk) within 2 mm of the package.
Stability checklist
– Verify phase margin > 45 ° using the op-amp’s open-loop gain/phase data.
– Isolate capacitive loads > 50 pF with a 10–50 Ω series resistor.
• Medical-device front ends must cap the closed-loop gain to prevent patient-hazardous saturation when electrodes disconnect (IEC 60601-1 §3.4).
• For high-impedance sensors, ESD protection diodes must not leak > 100 pA at 40 °C to avoid data drift.
• Cryogenic non-inverting stages (< 77 K) still struggle with GBW × slew-rate trade-offs; wide-bandgap SiC/JFET input stages are under investigation.
• AI-assisted resistor-network tuning is emerging to auto-compensate temperature-drift in precision gain blocks.
• Non-inverting op-amps deliver gain \(≥1\) with zero phase inversion and input impedances up to tera-ohms.
• Closed-loop gain is set by \(1+R_f/R_1\); bandwidth scales inversely with that gain.
• Modern rail-to-rail, zero-drift devices extend performance but may impose minimum-gain stability limits.
• Careful resistor sizing, impedance matching, decoupling, and PCB layout are decisive for low-noise, oscillation-free operation.
References
[1] “Non-Inverting Operational Amplifier,” Electronics-Tutorials.ws, 2024.
[2] Analog Devices Glossary: “Non-Inverting Op-Amp,” 2023.
[3] Texas Instruments, OPA388 Datasheet, Rev. E, 2023.
[4] Analog Devices, ADA4610-2 Datasheet, Rev. C, 2022.
[5] R. Mancini (ed.), Op Amps for Everyone, TI Literature SLAA068, 2023.
[6] Cadence PCB Blog, “Non-Inverting Op-Amp: Single-Supply Design,” Jan 2024.
[7] Texas Instruments, THS3491 Stability Application Note, Feb 2022.
