Tuya CB2S (BK7231N) Pinout, Wiring Diagram, UART Flashing, Power Supply

User question

cb2s baglantı şeması

Artificial Intelligence Response

Direct answer to the question

• The essential connections for the Tuya CB2S Wi-Fi module (BK7231N) are:
 – 3V3 (VCC, Pin 1) → regulated 3.0 … 3.6 V supply (nominal 3 V 3)
 – GND (Pins 3 & 15) → system ground
 – UART-TX1 (Pin 7) → RX of USB-to-TTL adapter
 – UART-RX1 (Pin 5) → TX of USB-to-TTL adapter
 – CEN (Pin 10, active-LOW) → momentarily pulled to GND to reset / enter boot-loader
• All pins are 3.3 V logic; never apply 5 V.
• A full pin-out table and typical flashing/embedded connection diagram are given below.

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Detailed problem analysis

1. Module overview
    The CB2S is a 24-pad castellated SMT module that integrates a BK7231N Wi-Fi SoC, 32 Mbit serial flash and PCB antenna. It exposes power, UART1, two ADCs and up to 15 multi-purpose GPIOs that can be mapped to PWM, I²C, SPI, etc.

2. Pin numbering & orientation
    • Reference is the official Tuya datasheet (rev. 2023-11). “TOP view” means antenna at the top, pads facing you.
     ┌─ ANTENNA ─┐ TOP VIEW 1◄──┴───────────┴──►12 24◄───────────────►13 └─────────────┘ (Pin-1 marking is a square pad)   

3. Comprehensive pin-out

Pad	Name	BK7231N IO	Default peripheral	Notes / remarks
1	3V3	–	–	3.0-3.6 V supply
2	P8	IO 8	PWM / GPIO
3	GND	–	–	Ground
4	P7	IO 7	PWM / GPIO
5	RX1	IO 10	UART1_RX	Needed for flashing
6	P6	IO 6	PWM / GPIO
7	TX1	IO 11	UART1_TX	Needed for flashing
8	ADC1	IO 23	ADC (0-1.0 V)	12-bit SAR
9	P24	IO 24	PWM / GPIO
10	CEN	–	RESET_N	Active-LOW reset / enable
11	P26	IO 26	GPIO / PWM
12	P15	IO 15	PWM / GPIO
13	P14	IO 14	PWM / GPIO
14	P9	IO 9	I²C-SDA (alt) / GPIO
15	GND	–	–	Second ground
16	P17	IO 17	PWM / GPIO
17	P16	IO 16	PWM / GPIO
18	P1	IO 1	SPI-CS / GPIO
19	ADC2	IO 21	ADC (0-1.0 V)	Optional; not bonded on all PCB revisions
20	P3	IO 3	SPI-MISO / GPIO
21	P0	IO 0	SPI-CLK / GPIO
22	P4	IO 4	SPI-MOSI / GPIO
23	P2	IO 2	I²C-SCL (alt) / GPIO
24	P5	IO 5	PWM / GPIO

4. Minimal flashing/boot-loader wiring

CB2S pad Purpose USB-TTL / Programmer
────────── ─────────────── ─────────────────────
Pin 1 3V3 → 3.3 V OUT (must supply ≥300 mA)
Pin 3 GND → GND
Pin 7 TX1 → RX
Pin 5 RX1 → TX
Pin 10 CEN —> push-button to GND (hold LOW, power-up, release)

Include a 0.1 µF ceramic and a 100 µF electrolytic between 3V3 and GND close to the module for brown-out immunity.

5. Typical embedded connection (production design)
   • Power rail: 3V3 with RC π-filter (10 Ω / 10 µF / 100 nF).
   • Reset: CEN pulled-up to 3V3 via 10 kΩ, routed to an MCU or user push-button.
   • Status LED: any unused PWM-capable pin (e.g. P24) → LED->R 330 Ω→3V3.
   • Relay drive: P7 / P8 via NPN or MOSFET gate.
   • I²C sensors: P2 (SCL) & P9 (SDA) with 4.7 k pull-ups to 3V3.

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Current information and trends

• Community firmware (LibreTiny, OpenBK, OpenBeken) actively support CB2S; their docs reflect the same pin map.
• New “CB2S-J” variant (2023) keeps the pad assignment but moves the antenna; layout above is still valid.
• Manufacturers increasingly switch to 1-T packaging of BK7231N-32UQFN; CB2S remains a drop-in RF-certified module to speed compliance (FCC ID 2ANDL-CB2S).
• OTA update chains (HTTP + TLS-1.2) are now part of the Tuya and LibreTiny stacks, reducing the need for physical flashing after first install.

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Supporting explanations and details

• Why CEN instead of EN/RST? BK7231N combines core enable and reset; pulling it LOW during power-up vectors the ROM boot-loader to UART1 at 115 200 Bd or 1 500 000 Bd (auto-detect).
• Logic-level tolerance: all GPIO are NOT 5 V tolerant; absolute max = 3.6 V.
• ADC scaling: internal 1.0 V reference, so divide external analog signals (≈ 3.3 V) with 220 k/68 k or similar.

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Ethical and legal aspects

• Using CB2S inside commercial products requires preservation of FCC/CE labelling unless antenna or enclosure conditions change.
• Flashing third-party firmware voids Tuya cloud key material; ensure GDPR/consumer-data compliance when collecting telemetry.
• Respect open-source licences (Apache-2.0 for LibreTiny, GPL-2.0 for OpenBK).

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Practical guidelines

1. Prototype phase
    – Hand-solder 30 AWG wires to the castellations or use a 1.27 mm pitch breakout PCB.
    – Verify supply ripple < 50 mVpp with an oscilloscope during Wi-Fi TX bursts.
2. Production PCB
    – Keep a solid ground pour under the module except under the antenna keep-out.
    – Route UART1 pads to a 4-pin tag-connector for future field re-programming.
3. Troubleshooting flashing
    – If connection logs show “Sync fail”, swap RX/TX or retry CEN timing.
    – Use FTDI FT232RL or CP2102 at 3 V 3; many CH340 clones droop below 2.9 V under load.

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Possible disclaimers or additional notes

• Datasheet revisions differ slightly in pin naming (P24 vs IO24); always cross-check with latest PDF (see source [7]).
• ADC2 (pad 19) is bonded only on rev-B silicon; earlier modules leave it NC.

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Suggestions for further research

• Evaluate BK7231T (Arm Cortex-M4F) + CB3S for higher throughput or BLE coexistence.
• Study Tuya’s “IoTOS V3.6” versus lightweight open stacks for power-saving (< 56 µA DTIM = 3).
• Investigate Matter-over-Wi-Fi porting on BK7231N (experimental in LibreTiny 0.8.0-dev).

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Brief summary

The CB2S module requires only five essential pads for power, ground and UART1 to flash or integrate into a design. Provide a clean 3.3 V rail, cross-connect UART signals, and control the CEN pin for reset/boot-loader entry. The full 24-pad pin-out, given above, lets you exploit PWM, ADC, SPI or I²C peripherals in production hardware while respecting 3.3 V limits and RF keep-out rules.

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