CPLD and FPGA are digital logic devices which are often confused. Let’s try to point out the most significant differences in architecture and features of both types of devices.
CPLD (Complex programmable logic device) is a non-volatile chip which contains features of both PALs and FPGAs. If it comes to complexity, it is between those two types of devices (less complex than FPGAs and more complex than PALs). Macro cell is the main building block of CPLD, what provides predictable timing characteristics. Simple architecture of CPLDs, which consist of relatively small number of large blocks of logic, has a positive effect on the speed of such devices’ operation. CPLDs are designed with the use of EEPROM, which affects their more predictable delays than in the case of FPGAs, and non-volatility of CPLDs as well. They are already active at power-up what can be an issue when you are concerned about the security of a design. Due to their status of less complex devices with simpler architecture than FPGAs, and thus their possible applications, CPLDs are relatively cheap, in comparison to FPGAs.
On the other hand, FPGA, which is a Field Programmable Gate Array, has a greater complexity due to its structure. Very important feature of being programmable makes its applications more flexible. It is RAM-based and needs configuring at every power-up, what can be quite demanding or even difficult for a less advanced user. FPGA contains many advanced and useful features for implementation of binary counters, arithmetic functions etc. What more, it can support large digital designs in comparison to CPLD, which supports only small designs. All these features make FPGA a perfect solution for more complex designs which require advanced functions and great flexibility.
CPLD (Complex programmable logic device) is a non-volatile chip which contains features of both PALs and FPGAs. If it comes to complexity, it is between those two types of devices (less complex than FPGAs and more complex than PALs). Macro cell is the main building block of CPLD, what provides predictable timing characteristics. Simple architecture of CPLDs, which consist of relatively small number of large blocks of logic, has a positive effect on the speed of such devices’ operation. CPLDs are designed with the use of EEPROM, which affects their more predictable delays than in the case of FPGAs, and non-volatility of CPLDs as well. They are already active at power-up what can be an issue when you are concerned about the security of a design. Due to their status of less complex devices with simpler architecture than FPGAs, and thus their possible applications, CPLDs are relatively cheap, in comparison to FPGAs.
On the other hand, FPGA, which is a Field Programmable Gate Array, has a greater complexity due to its structure. Very important feature of being programmable makes its applications more flexible. It is RAM-based and needs configuring at every power-up, what can be quite demanding or even difficult for a less advanced user. FPGA contains many advanced and useful features for implementation of binary counters, arithmetic functions etc. What more, it can support large digital designs in comparison to CPLD, which supports only small designs. All these features make FPGA a perfect solution for more complex designs which require advanced functions and great flexibility.
