is anyone knows how one half,ie one NMOS transistor let M1 or M2, of the differential amplifier will turned off during the operation.
Because during operation evenif it s a differential amplifier the input to the next stage will be Vdd and (Vdd-IssR1).So in any way both half or both the nmos transistor that is either through M1 or M2will be turned on .So how could we say that during operation the whole current Iss will flow through one transistor that is either through M1 or M2 .This is the problem that I'm not getting understood. Please help me
Because during operation evenif it s a differential amplifier the input to the next stage will be Vdd and (Vdd-IssR1).So in any way both half or both the nmos transistor that is either through M1 or M2will be turned on .So how could we say that during operation the whole current Iss will flow through one transistor that is either through M1 or M2 .This is the problem that I'm not getting understood. Please help me
Attachments:
