The problem is to design CMOS voltage pulse generator (based on the principle of ring oscillator) which fulfill certain condition: output frequency must be directly proportional to the width of single input pulse. That is to say, we have:
*Means:* 90nm CMOS technology, 1.2V transistors
*Input:* single pulse with duration between 1ns and 500ns
*Output:* pulses with duty cycle 50% and frequency (500MHz-1GHz) directly proportional to the duration of the input single pulse.
I designed VCO with frequency between 500MHz and 1GHz, but I can't figure out what to do next.
Please, give me some tips to complete this task.
*Means:* 90nm CMOS technology, 1.2V transistors
*Input:* single pulse with duration between 1ns and 500ns
*Output:* pulses with duty cycle 50% and frequency (500MHz-1GHz) directly proportional to the duration of the input single pulse.
I designed VCO with frequency between 500MHz and 1GHz, but I can't figure out what to do next.
Please, give me some tips to complete this task.
