STM32 ADC DMA Circular Mode: Triggering 100-Sample Conversion on Timer PWM Edge

I have configured the STM32 ADC in the DMA mode (circular) which fills a buffer, for example, a buffer with 100 elements (buffer[100])
I have set a timer to generate PWM pulse and I want that the falling edge of the PWM is used as the ADC trigger. I mean when the Timer or internal trigger happens, the ADC should do the conversion of all 100 samples, then it must wait for the next trigger to start the conversion again.
I don't want to use interrupts because interrupts could have unknown jitter or time shift, but in my case, I want to sample the input signal without any possible shift in the sampling and if I use the timer interrupt as a trigger (to start the ADC DMA), then some unwanted shifts in the conversions might happen, because the conversions start point is not a fixed number.
unwanted time shifts in the sampling should be as low as possible, even in the range of nS.
I use CubeMX.

Reading through your post I don't really see a question. Just a lot of statements about what you are doing. Assuming you are asking the best way to minimize jitter, the best thing to do would be to use the falling edge of the PWM to generate the interrupt that kicks off your DMA. Interrupts only have an overhead of 12 - 15 clock cycles and its deterministic. You would want to make sure that your interrupt is high priority so that it gets the CPU first. That should help you minimize the jitter. 

That's true because the interrupt might introduce a jitter which is not acceptable in this task.The question is what I can see from the triggering concept in the STM32 is not something like a start flag, but we should generate a clock to make a sampling sequence. for example for 100 samples, 100 pulses. the frequency of the pulses also should match with the desired ADC sampling frequency.What I'm looking is a real trigger, I mean just like a key to fire the sampling sequence, because I have already initiated the circular DMA to make 100 samples. after it's done, the ADC must wait for the next trigger to do the same.is it possible?

It may be possible but tricky. You will need an internal clock/timer where you can read the value. This clock/timer will need to have a time resolution that is better than the tolerable jitter. Then you set up a timer on an interrupt to time out shortly before you need to start the ADC. In the interrupt, you read the timer to find how long you have left then do a tight loop for that time before sending the command to start the ADC. The tight loop may have to be in assembly language and if your processor has pipelining, then you may have to disable it for the loop.Alternatively, you set up your PWM, set an interrupt before the PWM changes then read the PWM in a tight loop until it changes and start the ADC.Either of these will play havoc with any other timing you might want to do.In many ways it would be easier to do this in an FPGA.

In many ways it would be easier to do this in an FPGAYou mean making the clock for the trigger or ADC conversion inside FPGA?if you mean the clock, we can use another MCU or an accurate Crystal Oscillator.

By doing it in an FPGA, I mean you could generate the PWM signal, use it to trigger a sequence of ADC conversions including reading the ADC results and sending them to your MPU. Or you could have the MPU generate the PWM and use that to trigger the FPGA to do the ADC conversion sequence.  Some FPGAs have ADCs built in but they may not be good enough for your requirements.
High end FPGAs can include MCUs inside so you could potentially do everything in the FPGA. The high end parts are expensive though so you need to balance the cost with your other requirements.