Robust Solution for Miller-Induced Low-Side MOSFET Turn-On in Three-Phase Inverter (FDBL86062_F085)

I

I am facing an unintended turn-on issue in a three-phase inverter (half-bridge leg).
When the high-side MOSFET turns on, the switching node experiences a dv/dt as Vds of the high-side device falls rapidly. This dv/dt couples through the Miller capacitance (Cgd) of the low-side MOSFET. As a result, a positive voltage spike appears at the low-side gate, even though the gate driver is commanding it off.
This induced gate voltage rise causes momentary low-side turn-on, leading to shoot-through in the inverter leg.

Observations:
Under light-load conditions, the induced Vgs spike was initially around 2 V.
After tuning, I reduced the spike to approximately 0.8 V, which is below the threshold voltage and seems safe at low load.
However, when the load current increases, the gate voltage hump increases again and approaches the MOSFET threshold voltage. The issue becomes more severe at higher load current, likely due to increased di/dt and dv/dt.

Mitigation Steps Already Tried:
Increased gate turn-on resistance from 2.2 Ω to 33 Ω
Decreased gate turn-off resistance from 5.1 Ω to 2.2 Ω. Added external gate-to-source capacitor up to 15 nF
Tuned RC snubber across the switch.
Implemented an external Miller-clamp circuit using a PNP transistor MOSFET, part number (FDBL86062_F085-ONSEMI).

These methods reduced the spike under light load but did not fully eliminate the issue under higher load conditions.

What would be a robust and permanent solution to prevent Miller-induced turn-on of the low-side MOSFET at higher load currents?
AI: Could you provide details about the gate driver IC you are using (part number, source/sink current capability, and whether it has a built-in Miller clamp or other relevant features)?
Yes
AI: Can you share information about your PCB layout, specifically regarding gate drive trace lengths, gate loop inductance, and how the low-side source is referenced to the driver and power ground?
Yes

Hi.

vigneshrengaraj21120 wrote:

Increased gate turn-on resistance from 2.2 Ω to 33 Ω

This slows down the voltage build-up, but generates higher switching losses (switching losses).
Instead of a 2.2 Ω resistor for the switching diode, try putting 0.2-1Ω there and make sure you use a very fast Schottky diode.
Incorrect routing of paths is often the culprit.
Do you have a PCB layout?
What distances between the driver and the mosfet.
Are you using Kelvin type connections?

The ways are as you mentioned. I also had such difficulties I had to change the transistor to one with lower Qgd and higher Vgsth and the resistor in the gate circuit had to be increased to 220 ohms. I had a low Qg and this was acceptable. Increasing the resistor slows the turn-on and increases losses, you need to check on an oscilloscope that the turn-on speed is acceptable.
A 100% effective way is to use a driver that feeds a negative voltage. Drivers for IGBTs have such functions, but this requires a different power supply and a different high side control, you would have to rework everything.

vigneshrengaraj21120 wrote:

Increased gate turn-on resistance from 2.2 Ω to 33 Ω

Give more.

vigneshrengaraj21120 wrote:

Decreased gate turn-off resistance from 5.1 ohm to 2.2 ohm.

Driver output resistance is 1.1 ohm you can reduce R to zero. Check that you are using a low drop Schottky diode, a poorly sized diode can be over 1V when overloaded.

vigneshrengaraj21120 wrote:

An external Miller clamp circuit was implemented using a PNP MOSFET transistor, part number (FDBL86062_F085-ONSEMI).

And what was the PNP transistor? Did it have a high beta at high currents?

BobsonicLab wrote:

This slows down the voltage rise, but generates higher switching losses.

Switching losses always have to be compared with losses on Rdson. Sometimes people over-estimate the switching rate because they have not done the calculations. If the loss on Rdson is, for example, 1W then whether the switching loss is 100mW or 20mW is irrelevant, and lower du/dt also means fewer interference problems.

jarek_lnx wrote:

I also had such difficulties I had to change the transistor to one with lower Qgd and higher Vgsth and the resistor in the gate circuit had to be increased to 220 ohms

This is a classic example of a 'guerrilla' method and asking for spectacular fireworks rather than stable inverter operation.

jarek_lnx wrote:

Switching losses always have to be compared with losses on Rdson. Sometimes people over-estimate the switching rate because they have not done the calculations. If the loss on Rdson is, for example, 1W then whether the switching loss is 100mW or 20mW is not important, and lower du/dt also means less interference problems.

This is true, but for small currents.

The transistor will switch very slowly, spending a lot of time in the so-called active (linear) region.
With a large load current, the power loss at this short moment will be so high that it can burn up the mosfet.
Although the large resistor suppresses parasitic oscillations, in combination with such a large gate capacitance it creates a low-pass filter with a large time constant.

For on, you can experiment with values of 5-33 Ω to slow down the dv/dt (as you have already done).
For off, the resistance should be as low as possible (0-2.2 Ω) to give the driver gate control + a fast/ultra fast schottky diode.
A 220 Ω resistor is a step in the opposite direction to what you intended.

With resistor Rg=220 Ω and capacitance Ciss≈7 nF, the time constant τ (RC) is:
$$\tau_{total} = (R_{g(ext)} + R_{g(int)}) \cdot C_{iss}$$
$$\tau_{total}$$ : $$(220 \ \Omega + 0,4 \ \Omega) \cdot 7 \cdot 10^{-9} \ \text{F} \approx 1,543 \ \mu\text{s}$$
The 220 Ω proposal is almost 30 times greater than the geometric mean calculation.

Minimum resistance (critical attenuation):
$$R_{min} = \sqrt{\frac{L}{C}} = \sqrt{\frac{10 \cdot 10^{-9} \text{ H}}{6,97 \cdot 10^{-9} \text{ F}}} = \sqrt{1,435} \approx 1,20 \ \Omega$$

Geometric mean (optimum resistance):
$$R_{total} = \sqrt{Z \cdot R_{min}} = \sqrt{50 \ \Omega \cdot 1,20 \ \Omega} = \sqrt{60} \approx 7,75 \ \Omega$$

External resistance (Taking into account the internal resistance of the driver and the MOSFET transistor):
$$R_{ext} = R_{total} - R_{driver} - R_{g(int)} \approx 7,75 \ \Omega - 2,5 \ \Omega - 0,4 \ \Omega \approx 4,85 \ \Omega$$

-Input capacitance ($$C_{iss}$$ ): $$6970 \text{ pF}$$ .
-Internal gate resistance ($$R_{g(int)}$$ ): $$0,4 \ \Omega$$ .
-Gate-drain charge (key to the Miller effect) ($$Q_{gd}$$ ): $$20 \text{ nC}$$
-Threshold voltage ($$V_{GS(th)}$$ ): $$2,0 \text{ V} \dots 4,5 \text{ V}$$ .
-Path parasitic inductance (value assumed by design) ($$L$$ ): $$10 \text{ nH}$$

How much current will you be switching?
Layout pcb to be checked.

Added after 23 [minutes]:

The gate resistor (diode with resistor also) including the driver should be close to the gate of the mosfet transistor, use precision resistors tolerance ≤1% and temperature coefficient TCR≤100 ppm/°C.

BobsonicLab wrote:

This is a classic example of the "guerrilla" method and asking for spectacular fireworks rather than stable inverter operation.

220 ohms is a lot, I give this as an extreme case and not a suggestion for a transistor that has a Qgd of 20nC It was checked, the transistor had a small enough Qg that the Miller plateau did not last longer than 10% of the period. The type of transistor I can hardly recall the inverter was on just 4A 12V

jarek_lnx wrote:

BobsonicLab wrote:

This is a classic example of a "guerrilla" method and asking for spectacular fireworks rather than stable inverter operation.

220 ohms is a lot, I give this as an extreme case and not a suggestion for a transistor that has a Qgd of 20nC It was checked, the transistor had a small enough Qg that the Miller plateau did not last longer than 10% of the period. The type of transistor I can hardly recall the inverter was on just 4A 12V

Phew, sorry... Miller plateau lasted a short time, then the transistor quickly jumped through the linear region, low power losses and the chassis quietly dissipated them.
We don't know what currents the author of the post wants to operate at, as it doesn't look like 4 A 12 V (48 W). If he doesn't specify we won't know . We also don't know what the PCB looks like, and it's usually poorly routed paths that cause a number of problems.

Thank you everyone for your valuable suggestions and ideas.

The operating voltage of the inverter is 58 V, and the continuous current is around 60 A. I am currently working on reducing the Miller-induced voltage. My understanding is that using a larger gate-to-source capacitance can act like a charge reservoir (bucket), making it harder for the dV/dt to change the gate voltage unintentionally. This seems to be helping — please let me know if this approach looks correct.

Additionally, I am facing another issue: the phase node appears to be floating when the system is idle (power on with 58 V). After investigation, I suspect this is due to internal gate driver leakage. Has anyone experienced a similar issue? What methods did you use to mitigate it? If I place 10 kΩ across phase to ground, the floating voltage vanishes; once removed, it floats again...

vigneshrengaraj21120 wrote:

Additionally, I am encountering another problem: the phase node seems to float when the system is idle (power on at 58V). After investigating, I suspect this is due to an internal gate driver leak. Has anyone experienced a similar problem? What methods have you used to mitigate it? If I put 10 kΩ between phase and ground, the floating voltage disappears; when removed it rises again...

This phenomenon is normal in half-bridge circuits. When both transistors are off, the phase node is in a high-impedance state. Minimum leakage currents of the order of microamperes from the controller or the MOSFET transistors themselves charge the parasitic capacitances of the node. At a rail voltage of 58 V, even 1 μA of leakage will quickly raise the potential of the 'hanging' path.
You may want to check larger values than 10 kΩ.

Added after 5 [minutes]:

Can you post the layout of the PCB or a picture? We're not going to bode from the fushe 😅 what may or may not be the problem. A path of error elimination is needed to improve performance; bad routing of paths we can't rule out.