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icastaneda7 wrote:

(+) -----[R1]-----[R2]----- (-)

Added after 1 [hours] 50 [minutes]:

It seems like you're describing a simple resistive circuit with two resistors (R1 and R2) connected in series between a positive terminal (+) and a negative terminal (-). This is a basic voltage divider circuit, which is commonly used in electronics to reduce a voltage to a desired level.

Voltage Divider Circuit Overview

A voltage divider is a linear circuit that produces an output voltage (Vout) that is a fraction of its input voltage (Vin). The output voltage is taken from the junction between the two resistors.

Circuit Diagram



Key Components:
- R1 and R2: Two resistors connected in series.
- Vin: The input voltage applied across the series combination of R1 and R2.
- Vout: The output voltage taken from the junction between R1 and R2.

Formula for Output Voltage:
The output voltage (Vout) can be calculated using the following formula:

$$ V_{out} = V_{in} \times \frac{R2}{R1 + R2} $$

Example Calculation:
Let’s assume:
- Vin = 12V
- R1 = 10kΩ
- R2 = 5kΩ

Using the formula:

$$ V_{out} = 12V \times \frac{5kΩ}{10kΩ + 5kΩ} = 12V \times \frac{5}{15} = 12V \times 0.333 = 4V $$

So, the output voltage (Vout) would be 4V.

Applications of Voltage Divider:
- Level Shifting: Reducing a higher voltage to a lower level suitable for other circuits.
- Sensor Circuits: Reading sensor outputs that vary resistance with changes in the measured quantity (e.g., light, temperature).
- Biasing: Providing bias voltages in amplifier circuits.

Practical Considerations:
- Power Dissipation: Ensure that the resistors can handle the power dissipation, calculated as $ P = V^2 / R $.
- Loading Effects: If a load is connected to Vout, it will affect the output voltage. To minimize this, the load resistance should be much larger than R2.

Would you like more information on how to choose resistor values or how to apply this circuit in a specific application?

paul41014paul wrote:

https://obrazki.elektroda.pl/2386332400_1756431901.png @ElektrodaBot

Initial assessment of available information
- You pinged @ElektrodaBot several times and earlier asked for “Design a monostable trigger.”
- You also posted a simple series divider (+)—R1—R2—(−) and, more recently (May 03, 2025), a two‑stage NPN amplifier LTspice netlist powered from 12 V.
- To move you forward quickly, I provide a complete, ready‑to‑build monostable (one‑shot) design first, then short notes on your series divider and on the amplifier netlist you shared.

Direct answer: two robust monostable trigger designs
Below are two proven topologies. Choose based on supply voltage, accuracy, and whether you want retriggering.

1) 555‑based monostable (simple, can drive relays/LEDs directly)
- Supply: 5–15 V (fits your 12 V environment).
- Trigger: active‑low pulse on pin 2 (must fall below ~1/3 VCC for >10 µs for a bipolar NE555, shorter for CMOS types).
- Pulse width: T ≈ 1.1 × R × C (seconds if R in ohms, C in farads).
- Retriggerable: yes (additional triggers while output is high extend the pulse).
- Wiring summary:
- Pin 1 to GND, pin 8 to +V.
- Pin 4 (RESET) tied to +V via 10 kΩ (prevents power‑up false resets).
- Pin 5 (CTRL) to GND via 10 nF (noise immunity).
- R from +V to pin 7.
- C from pin 6 to GND.
- Pin 2 and pin 6 tied together at the RC junction (this node is your timing node).
- Output on pin 3.
- Decoupling: 100 nF ceramic close to pins 1–8 plus 10 µF electrolytic on the rail.
- Example for a 1.0 s pulse at 12 V, nonprecision:
- R = 910 kΩ (1%), C = 1.0 µF film or low‑leakage electrolytic → T ≈ 1.1 × 0.91 M × 1 µF ≈ 1.0 s.
- If you need better stability, prefer a CMOS 555 (TLC555/LMC555) and a film capacitor; keep R between 10 kΩ and 2 MΩ to limit leakage sensitivity.
- Switch/logic trigger suggestions:
- From a pushbutton: add a 10–100 nF cap from pin 2 to GND and a 100 kΩ pull‑up to +V (simple debounce).
- From a higher‑voltage or noisy source: trigger via an NPN transistor (collector to pin 2/6, emitter to GND, base through 10–47 kΩ from your signal) and keep a 100 kΩ from pin 2/6 to +V.

2) Comparator/Schmitt one‑shot (accurate, wide timing range)
- Use a rail‑to‑rail comparator with hysteresis (e.g., any modern low‑power comparator) or a Schmitt inverter (74HC14).
- Topology (non‑retriggerable): RC from output to the inverting input (Miller one‑shot), trigger edge applied through a small capacitor and series resistor to the non‑inverting input; set thresholds with a divider to mid‑supply and add hysteresis (positive feedback).
- Pulse width: T ≈ k × R × C, where k depends on the chosen hysteresis ratio (commonly ~0.69 for symmetric ± thresholds).
- Benefits: clean edge detect, defined thresholds, excellent drift if you use C0G/NP0 capacitors and 1% resistors.
- Choose this if you need sub‑millisecond to seconds accuracy, 3.3/5 V logic compatibility, or a strictly non‑retriggerable output. A single‑gate monostable like 74LVC1G123/HC123 is also an elegant “one‑chip” solution (internally timed, edge‑triggered, selectable retrigger).

Detailed engineering guidance
- Define requirements before picking parts:
- Supply and logic levels (you showed 12 V in other posts; confirm if 5 V is an option).
- Trigger characteristics (edge or level, active polarity, debounce needed).
- Pulse width range and tolerance (e.g., 1.0 s ±5%).
- Retrigger behavior: extend pulse on new triggers, or ignore them until completion.
- Component selection tips:
- Timing capacitor: for milliseconds, use C0G/NP0 ceramic; for ≥100 ms, use film (polypropylene/polyester). Electrolytics are acceptable for long pulses but introduce ±20% tolerance and temperature drift.
- Timing resistor: 10 kΩ to 2 MΩ is a good window. Higher values magnify leakage effects; lower values increase supply current.
- Output drive: NE555 can source/sink tens of milliamps; for coils or motors use a transistor or MOSFET with a flyback diode.
- Noise and reliability:
- Keep the timing node short, shielded from switching currents.
- Add a 100 nF local decoupler right at the IC.
- For automotive‑like 12 V rails, add a series 10 Ω with 100 µF + TVS if transients are expected.
- Power‑up behavior:
- 555s can self‑trigger at power‑up. A 100 nF from RESET to GND and 100 kΩ from RESET to +V produces a clean start.

Practical “bill of materials” examples (12 V system)
- 50 ms: R = 100 kΩ, C = 470 nF → ~52 ms.
- 500 ms: R = 470 kΩ, C = 1.0 µF → ~0.52 s.
- 5 s: R = 1.0 MΩ, C = 4.7 µF → ~5.2 s (prefer CMOS 555; use film or quality electrolytic).

Testing and verification
- Bench check with a scope: confirm trigger crosses the 1/3 VCC threshold and timing node ramps to 2/3 VCC in T seconds.
- Try worst‑case extremes: cold/hot, ±10% supply.
- In SPICE, include capacitor leakage (use a parallel large resistor, e.g., 50–200 MΩ for electrolytics) to see long‑pulse drift.

Short notes on your earlier posts
- Series divider (+)—R1—R2—(−):
- Vout at the midpoint (to the negative rail) is Vin × R2/(R1+R2).
- If you connect a load to Vout, it is in parallel with R2; recompute using Req = (R2‖Rload). Keep Rload at least 10× R2 to minimize error.
- Two‑stage NPN amplifier netlist from 03/05/2025:
- Q2 is missing a defined emitter bias (E2 node not tied through a resistor to ground or a supply). Add an emitter resistor to set emitter current, and a base divider to bias B2 around 0.6–0.8 V above the emitter.
- A typical 12 V CE stage at ~1 mA: RC ≈ 4.7–10 kΩ to place VC near 6 V; RE ≈ 680–1.2 kΩ for thermal stability; base divider to set VB ≈ VE + 0.65 V; coupling capacitors sized for the lowest frequency of interest (fC ≈ 1/(2πRinC)).
- Don’t forget rail decoupling (100 nF + 10 µF) and, if you want maximum gain, an AC bypass across RE sized so that 1/(2π RE‖Rsig Cbypass) is a decade below your passband.

Ethical and safety aspects
- When driving inductive loads from the monostable, always add a flyback diode across the coil.
- If any part interfaces with external wiring, consider ESD protection and proper isolation as per your local regulations.

Suggestions for further research
- Compare NE555 vs. CMOS 555 datasheets for trigger thresholds and supply currents.
- Look at dedicated monostables (HC123/LVC1G123) for logic‑level designs needing tight tolerance and built‑in edge detection.

Brief summary
- For a fast, strong one‑shot in a 12 V system, a 555 monostable with T = 1.1RC is the simplest and most robust solution.
- For tighter timing or logic‑level systems, use a comparator/Schmitt topology or a logic monostable (74HC/LVC x123).
- Your posted amplifier needs proper biasing of the second stage; I can provide exact values once you define gain and bandwidth.

Questions for you
1) Supply and logic levels available (5 V, 12 V)?
2) Required pulse width and tolerance; retriggerable or not?
3) Trigger source (mechanical switch, sensor, microcontroller pin, noisy line)?
4) Load you need to drive (logic input, LED, relay, MOSFET gate)?
5) For the amplifier netlist: target gain and bandwidth?

Share these details and I’ll deliver a finalized schematic with exact values and an LTspice file tailored to your application.