Creating NF vs Current Density Plots in Cadence for CMOS LNA Design

Sunnysky wrote:

(...) logarithmically, it seems the sweep variable must be the drain current instead of gate voltage, but if I vary the drain current with a current source how do I set an appropriate gate voltage? https://obrazki.elektroda.pl/8377485500_1704318777.png
https://obrazki.elektroda.pl/5101176500_1704318803.png

Hello there,

Creating those noise figure versus current density plots requires some simulation setup that involves both sweeping the bias conditions and extracting the noise figure at each point. Let's walk through the steps you'd need to take in Cadence to obtain the necessary data and generate the plots.

Firstly, your simulation setup looks decent for a basic noise figure (NF) simulation. You have a single transistor with biasing and matching networks, which is a good starting point. However, to plot NF versus current density, you need to extract the drain current ($$I_{DS}$$) for each gate-source voltage ($$V_{GS}$$) you sweep.

Here's how you can approach it:

1. In your simulation environment, you're rightly performing an S-parameter simulation with noise analysis enabled. From this, you'll get the NF versus $$V_{GS}$$.

2. Now, to extract $$I_{DS}$$ as a function of $$V_{GS}$$, you will need to add a DC operating point analysis (DC OP) to your simulation. This will allow you to extract the current flowing through the drain of your transistor at each $$V_{GS}$$.

3. With the DC OP analysis, you can create a parametric sweep of $$V_{GS}$$ and at each step extract both the NF (from S-parameter analysis) and $$I_{DS}$$ (from DC OP analysis).

4. Then, to plot NF versus current density ($$I_{DS}/W$$), you'll calculate the current density by dividing each extracted $$I_{DS}$$ by the total gate width.

Here's a more detailed step-by-step for your simulation setup:

A. Adjust your setup to include both S-parameter analysis with noise and a DC operating point analysis.
B. Perform the sweep over $$V_{GS}$$ and record both NF and $$I_{DS}$$ for each $$V_{GS}$$.
C. Post-process the data to calculate $$I_{DS}/W$$ for each step, where $$W$$ is the total gate width of your transistor.
D. Plot NF versus $$I_{DS}/W$$ using a data visualization tool of your choice (e.g., MATLAB, Python with Matplotlib, or even the built-in plotting tools in Cadence if available).

As for the concern about varying the drain current logarithmically:

1. You can indeed sweep $$I_{DS}$$ directly by using a current source at the drain and stepping its value.
2. For each $$I_{DS}$$ value, you would adjust $$V_{GS}$$ to maintain the desired drain current. This could be done by employing a feedback control mechanism in your test setup or via an iterative simulation process where you manually tune $$V_{GS}$$ until the desired $$I_{DS}$$ is achieved for each step.

Remember, the goal is to capture the relationship between NF and the bias conditions of your transistor, and there can be more than one way to do it. If your simulator allows it, you might find a more automated way to do the sweep and data extraction.

Would you like to discuss how you could implement a feedback control in your test setup to maintain a constant $$I_{DS}$$ or any other aspect of the simulation process in greater detail?

Sunnysky wrote:

anything else?

Certainly! There are a few additional considerations to ensure accurate simulation and result interpretation:

1. Device Modeling and Calibration: Make sure the transistor model you are using is well-calibrated for the 22nm CMOS process, especially for RF and noise characteristics. Model parameters can significantly impact noise figure calculations.

2. Biasing Network: Ensure that the biasing network does not significantly contribute to the noise figure. You might need to simulate the bias tees to verify their noise contribution is minimal or accounted for in the simulation.

3. Frequency Dependence: You mentioned plotting NF versus current density irrespective of frequency, but in reality, NF can have a strong frequency dependence. Make sure to simulate at the actual frequency of interest for your LNA design.

4. Output Matching: While the input matching is critical for NF, don't overlook the output matching. It can affect the overall gain and stability, which in turn can influence the perceived noise figure due to mismatch losses.

5. Temperature: Noise is temperature dependent. Set the simulation temperature to the expected operating temperature of your LNA.

6. Process Variations: It's good practice to simulate across process corners (slow, typical, fast) to see how process variations might affect your NF versus current density plot.

7. Power Consumption: While reducing NF is essential, don't neglect the power consumption. Make sure the operating point you choose is a good compromise between NF and power efficiency.

8. Sweeping Strategy: When sweeping $$V_{GS}$$, it's important to ensure that the device is operating in the correct region (usually the saturation region for an LNA). Check the $$V_{DSsat}$$ parameter to make sure the transistor isn't slipping into the triode region at any point in your sweep.

9. Data Processing: After the sweep, consider using a script to automate the data extraction and plotting. Tools like Python with Pandas and Matplotlib libraries can be very efficient for this kind of post-processing.

10. Validation: Lastly, consider validating your simulation results against a simple analytical model or empirical results if available. This can give you confidence in your simulation setup and results.

Would you like assistance with any specific part of your setup or simulation process? Or perhaps, do you have any other concerns or questions regarding your LNA design that you would like to discuss?

Sunnysky wrote:

I am trying to simulate a chart with conversion efficiency of a rectenna but so far the info i have been reading online is for circuits which don't match with what I am working with.
What formula for conversion efficiency can i use on the following schematic. https://obrazki.elektroda.pl/3576703700_1704322490.png

In the context of rectennas, the conversion efficiency ($$\eta$$) is typically defined as the ratio of the DC power delivered to the load to the RF power received by the antenna. For the given schematic, which appears to be part of a rectenna system with a diode-based rectifier, we can calculate the conversion efficiency using the following formula:

$$\eta = \frac{P_{DC}}{P_{IN}}$$

Where:
- $$P_{DC}$$ is the output DC power at the load (after the rectifier).
- $$P_{IN}$$ is the input RF power at the rectifier input.

From your schematic, the input power ($$P_{IN}$$) is defined by the source $$P_{Tone}$$. The output power ($$P_{DC}$$) can be calculated by measuring the voltage across the load resistor ($$R_L$$) and using the formula:

$$P_{DC} = \frac{V_{out}^2}{R_L}$$

Here's how you can simulate this in a circuit simulator like Keysight ADS (Advanced Design System), which your schematic seems to be designed for:

1. Run the Harmonic Balance Simulation: Since you're using a non-linear component (diode), you'll need to run a harmonic balance simulation to accurately predict the behavior of the circuit at your frequency of interest (9 GHz).

2. Measure $$V_{out}$$: Place a voltage probe or use a voltmeter component to measure the DC voltage across $$R_L$$.

3. Calculate $$P_{DC}$$: Use the measured $$V_{out}$$ and the value of $$R_L$$ to calculate the DC power. In many simulators, you can set up equations or use a calculator tool to perform this calculation automatically.

4. Input Power $$P_{IN}$$: Ensure that the source $$P_{Tone}$$ is set to the right power level (as per your design or experiment).

5. Calculate $$\eta$$: Finally, calculate the conversion efficiency using the formula provided above, again possibly using the simulator's equation or calculation tools.

Note that in practice, the conversion efficiency also depends on the impedance matching between the antenna and the rectifier, the diode's characteristics, and the quality factor of the passive components. The diode's IV curve, series resistance, and junction capacitance play a significant role in determining the rectifier's performance.

Additionally, it's important to consider the losses in the circuit, including any series resistance in the inductors and parasitic elements that are not shown in your schematic but can be crucial in real-world implementations.

Would you like to go into further detail about any particular part of your simulation or any specific concerns you have about your rectenna design?