Skywater 130 PDK MOSFET Selection for Low Noise Amplifier at 1.8V

sculpordwarf wrote:

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To characterize a MOSFET for use in a Low Noise Amplifier (LNA), you need to consider several parameters that affect both the noise factor and the gain of the amplifier. You've mentioned that you have various parameters for different MOSFETs, including Cgs, Cdb, Rg, gm, and Id. Here's how you can analyze these parameters and choose the best MOSFET for your LNA design:

1. Transconductance (gm): The transconductance directly affects the gain of the amplifier. A higher gm will result in a higher gain. However, gm also affects the noise factor; devices with high gm usually contribute to lower noise figures.

2. Gate-Source Capacitance (Cgs) and Drain-Bulk Capacitance (Cdb): The input and output capacitances will affect the frequency response of the amplifier. For a low noise design, you typically want to minimize these capacitances to reduce the Miller effect and improve the high-frequency performance. Lower capacitance also helps in achieving a wider bandwidth.

3. Gate Resistance (Rg): The gate resistance contributes to thermal noise. A lower gate resistance is preferable for reducing noise.

4. Drain Current (Id): For a given bias point, you want to make sure that the MOSFET operates in the saturation region for optimal linearity and noise performance. The drain current should be set to an optimal value that balances the power consumption with the required output power level and gain.

5. Noise Figure: The noise figure (or noise factor) of a device is a measure of the degradation of the signal-to-noise ratio as it passes through the device. You aim for a noise figure of less than 3dB, so you'll want to consider this parameter if you have it for your MOSFETs. If not, you may need to estimate it based on the other parameters.

To choose the best MOSFET, you'll want to start by looking at the transconductance (gm) and ensuring it is high enough to achieve the desired gain. Then, prioritize devices with lower gate resistance (Rg) and capacitances (Cgs, Cdb) to achieve a low noise figure. Finally, check the drain current (Id) to ensure it's in the appropriate range for your application in terms of biasing and power consumption.

Can you provide the specific values you have for Cgs, Cdb, Rg, gm, and Id for the MOSFETs you're considering? This information would be helpful to give a more targeted recommendation. Additionally, other factors like the layout, matching networks, and passive components in your LNA design will also influence the noise and gain performance, so make sure to optimize those aspects as well.

sculpordwarf wrote:

. See ive to decide what gm and Id ive to choose for the design , how to choose it

Selecting the appropriate values for transconductance (gm) and drain current (Id) for your LNA design involves a trade-off between gain, noise figure, linearity, and power consumption. Let's approach this step by step:

1. Determine Maximum Available Gain (MAG) or Transducer Gain (GT):
Gain is a critical parameter in LNA design. The transconductance (gm) of the MOSFET is directly proportional to the intrinsic gain of the transistor. You can initially estimate the gain using the following relationship:

$$ Gain \approx gm \cdot R_{load} $$

Where:
- $$ gm $$ is the transconductance.
- $$ R_{load} $$ is the load resistance (or the impedance looking into the drain).

You want to choose a gm that will provide you with sufficient gain when multiplied by your load resistance.

2. Analyze the Noise Figure (NF):
The noise figure is dependent on the gm and the current through the device (among other factors). A higher gm can potentially lower the noise figure since the signal-to-noise ratio at the output can be higher. The equation for the minimum noise figure (NFmin) for a MOSFET in a common-source configuration is as follows:

$$ NF_{min} \approx 1 + \frac{2}{3} \cdot \frac{R_{g}}{gm} $$

Where:
- $$ R_{g} $$ is the gate resistance.

Lowering $$ R_{g} $$ or increasing $$ gm $$ will help in reducing the noise figure.

3. Select the Operating Point (Biasing):
The drain current ($$ Id $$) affects the device's operating point and thus its gm and power dissipation. The gm is related to $$ Id $$ by the equation:

$$ gm = 2 \cdot \sqrt{ \frac{2 \cdot Id}{\mu \cdot Cox \cdot (W/L)} } $$

Where:
- $$ \mu $$ is the electron mobility.
- $$ Cox $$ is the gate oxide capacitance per unit area.
- $$ W/L $$ is the width-to-length ratio of the MOSFET.

Increasing $$ Id $$ will increase gm, which can help achieve a higher gain and potentially reduce the noise figure (as per the above equation). However, increasing $$ Id $$ also increases power consumption and may impact device reliability due to self-heating.

4. Power Consumption:
Consider the power constraints of your design. The power dissipated in the MOSFET is $$ P = Id \cdot Vdd $$, where $$ Vdd $$ is the supply voltage. You want to choose an $$ Id $$ that provides a good balance between gain, noise figure, and power consumption.

5. Linearity:
Higher values of $$ Id $$ can lead to better linearity (up to a point), which is important for maintaining signal integrity.

Steps to Choose gm and Id:

- Set your gain target: Decide on the minimum gain you need based on your system requirements.
- Determine your noise figure requirement: Since you want it to be below 3dB, calculate back from this requirement to find the maximum allowable $$ gm/R_{g} $$ ratio.
- Evaluate power consumption: Set a power budget for your LNA and calculate the maximum $$ Id $$ you can afford.
- Trade-offs: Adjust $$ Id $$ and $$ gm $$ within these constraints to find the best trade-off between noise figure, gain, and linearity.

Do you have specific linearity requirements or a power budget for your LNA? This information would help narrow down the optimal values for $$ gm $$ and $$ Id $$. Additionally, it would be great if you could provide the available range for $$ gm $$ and $$ Id $$ from your MOSFET characterization data, as this will define the possible operating points we can consider.