How to feed a 10Gbps signal into a 4:1 MUX using Simulink component

The basic transmitter is composed of three components: a CML (current mode logic) multiplexer, a CML buffer, and the CML driver itself. The link operates at 10 GHz, which is faster than typical CMOS clock speeds for this process, multiplexing is required to combine slower data into one 10 GHz bit stream. Assuming the CMOS clock is 2.5 GHz, the CML 4x1 multiplexer drives four bits every 2.5 GHz cycle. Four 2.5 GHz clock phases are the selection signals to the multiplexer. For example, when phases 0 and 1 are high, bit 0 is selected by the multiplexer. When phases 1 and 2 are high, bit 1 is selected. The multiplexer performs an “AND” operation of two phases to simulate having a clock with a 25% duty cycle. Question (1) How will a signal (for example NRZ) generated at 10Gbps be divided into four 2.5 Gbps and fed into the 4 channels of the MUX ?What are the components and how to implement in Simulink. Is it called a SERIALIZER Question (2) What is the function of FIR and how to use it in SIMULINK. Question (3) What will be the properties and parameter values of the Coaxial Transmission component in Simulink for this case and in general how does one decide. Please help.

This paper will start you off in the right direction.

Thank you , but my Question is actually based on this paper! It mentions sending a 10Gps signal into 4 channels of the MUX 4 bits at a time. How does one achieve this through a circuit? Thank you once again for your patience.

What part of the circuit are you having trouble with? The signal driving the MUX? Also are you looking to build this or simulate it in Simulink?

I am trying to just simulate the communication in matlab's simulink. The trouble is in driving the MUX. I am unable to figure out how to feed in a 10gbps signal (say NRZ) into each of the 4 channels of the MUX inputs (4:1 MUX)and also acheive the reverse when recovering the signal at the receiver section. Is there a general circuit so that I can scale it for other signals of say 20Gbps,40Gbps etc for different MUX say 2:1 etc. Further, what should be the Sample per second field in the Discrete eye diagram block for 10Gbps signal?

Ok lets start with the mux select. You will want a basic counter to cycle through the different mux channels. For example (00,01,10,11) or better yet (00,01,11,10) because this order could be created with a high speed signal and a 90º phase shifter version. I would also use Flip Flops before and after the mux.

Check out the two diagrams that are attached. I have created one that shows a circuit and the other shows the high speed signal and the phase shifted version to create the counter 00,01,11,10.

Hi, I went through the diagram which you provided but I dont think this is what I wanted to do !! The question was to feed in a 10Gbps signal into each of the 4 channels of the 4:1 MUX. I am sure that the entire 10Gbps signal would not be fed, but it should be divided equally for each of the input channel.Similarly, the reverse for the 1:4 MUX at the receiver section. Does the diagram achieve the same?

You asked:

"I am unable to figure out how to feed in a 10gbps signal (say NRZ) into each of the 4 channels of the MUX inputs (4:1 MUX)"

As I read between the lines of your post. I think that your confusing MUX with a DEMUX (demultiplexer).

One way to separate the bits at the receiver would be to use a shift register that has a flip flop on the output. The shift register clocked would have to be twice the frequency of the sampled signal. And the shift register output flip flops would be 1/4 that frequency if it was 4 channels.