Clock and Shift Register Setup for Dual Signal 16-bit ADC to DAC Conversion Project

hi there, I'm working on a small college project and got a little confused regarding some of the wiring and clock management. project consists on AD converting two separate signals, sending them through one channel together and recovering the analog signal like this https://imgur.com/Q2j0Tsa

so far, that's where I've managed to go https://imgur.com/COSHoQd

and my doubts are: does the clock makes sense? 16bits serial in, so it has to 16x faster, right (and since there are no 16bit registers, I strung two together)? should I shift right before my 16bit, so I can have all the 16bits available for conversion, or just parallel load it all and wire the DAC that way as displayed above?

I'm very rusty with digital electronics, and everything I have is based on 8bits tops, and only one signal. Filtering at the end is ok, I have already made a model for that and I plan just to set the correct component values to get my desirable signals. Clock and shift registers are killing me.

Icaro,

Sorry for the delay in response. Unfortunately, at my work when I first saw this, the site for your images was blocked by them. So I have to find time at home to answer.

In your first picture, it looks like you are to have two analog inputs and two analog outputs. So you need to have two DAC for output instead of one.

You have generally the right idea to do the ADC conversion and then shift the data out to the other side but your implementation looks a bit off. It's hard to read because the picture is small but I usually see a clock divider as making the clock slower instead of faster. So your clock input needs to be at the 16x rate to clock the shift registers then divided down to trigger the ADC converter and latch the data in the shift register. Or you need a clock multiplier to create the 16x clock

Then at other side you need to reverse it. Shift the 16 bits into two shift registers and then latch the outputs and send to the two DAC.

It looks as if you are allowed only one clock signal for communication to go with the data so you will need a clock divider on the output side as well. And then the problem will be how to get the two clock in sync.

I hope that this is helpful and that you have success with your project.

First, I'd like to thank you for the help! It's been very enlightening, and I learned more here than with my instructor's so far.So, I tinkeredit a little bit and got this far: 16 bits through 1 channel with 1 sync channel
I made a counter with a comparator logic to get the shifting going on my Tx end, but I'm not sure if they both should be at the same rate, my scopes can only get the readings for one signal.Still lost at how it works in the Rx end. 16x faster there? I'm not sure if I got this right, but I need to add latch flip flops too (before the DACs)?
Oh, and btw, if you feel like taking a look at it in multisim, here is the linkhttps://drive.google.com/file/d/1QhMWhmJDAQtWjuO7tXq4fkGW7_bz23kD/view?usp=sharing