FAQ
TL;DR: To get a basic NPN/PNP emitter follower working, fix the PNP pinout and use ≥1.2 Vp‑p drive; “you will have a very distorted output with what is called crossover distortion.” [Elektroda, Anonymous, post #21679598]
Why it matters: This FAQ helps beginners diagnose why their simple push‑pull amplifier in Multisim won’t swing or looks too perfect, and how to reveal and fix crossover distortion.
Who it’s for: Students and hobbyists asking “how do I fix my NPN/PNP Multisim test amp?”
Quick Facts
- Correct PNP wiring: emitter tied to NPN emitter; collector to the negative rail (e.g., −6 V). [Elektroda, Anonymous, post #21679598]
- Minimum drive without bias: ≈0.6 V per base-emitter, so ≈1.2 V peak‑to‑peak across the pair. [Elektroda, Anonymous, post #21679598]
- Expect crossover distortion near 0 V until biasing is added. [Elektroda, Anonymous, post #21679598]
- Add an output load (e.g., 10 kΩ to ground) so the sim shows realistic behavior. [Elektroda, Anonymous, post #21679601]
- In LTspice, 1–2 Vp‑p drive makes the distortion obvious; large drive can mask it. [Elektroda, Anonymous, post #21679605]
Why wont my output go positive in this NPN/PNP test stage?
Your PNP is reversed. Connect the PNP emitter to the NPN emitter node, and its collector to the negative supply (e.g., −6 V). That corrects the push‑pull pair so the positive half‑cycle comes through. “This will form what is called a complimentary push‑pull amplifier.” [Elektroda, Anonymous, post #21679598]
How much input amplitude do I need if there 19s no bias network?
About 0.6 V per transistor before conduction, so plan on ≈1.2 V peak‑to‑peak at the input to see clean transfer. Anything below that falls in the dead zone and won’t conduct. Expect visible distortion around zero crossing without added bias. [Elektroda, Anonymous, post #21679598]
What is a complementary pushpull amplifier?
A stage that pairs an NPN and a PNP emitter follower sharing the same emitter node. The NPN sources current for positive swings; the PNP sinks current for negative swings. Correct pin orientation is essential for symmetry and headroom. [Elektroda, Anonymous, post #21679598]
What is crossover distortion in this circuit?
It’s the flat spot at the waveform’s zero crossing where neither transistor conducts. With no bias, each device needs ~0.6 V V_BE, creating a ~1.2 V no‑conduction region. “You’ll get a nice horizontal kink in your sine wave at the crossover point.” [Elektroda, Anonymous, post #21679598]
How can I reduce crossover distortion here?
Add proper bias so both transistors are slightly on around 0 V. A small quiescent conduction removes the dead zone and linearizes the handoff between devices. This is why hi‑fi designs pay close attention to bias. [Elektroda, Anonymous, post #21679598]
Why does Multisim show a perfect sine with no distortion?
One user reproduced your circuit and Multisim showed no crossover distortion at all, which is unrealistic. Simulation settings, models, or missing real‑world elements can hide the artifact. Treat a too‑perfect sine as a red flag. [Elektroda, Anonymous, post #21679600]
Do I need a load resistor on the output in simulation?
Yes. Add a load (e.g., 10 kΩ from the emitters to ground). Without a load, the sim can look idealized and miss the crossover behavior. A realistic load helps the solver reveal non‑ideal transfer. [Elektroda, Anonymous, post #21679601]
Multisim still looks wrong. Could my source be the issue?
It can be. A function generator behaving like a current drive or odd source impedance skews results. Try replacing it with a DC source or check generator settings to confirm voltage drive behavior. This edge case can hide distortion. [Elektroda, Anonymous, post #21679602]
What drive level makes distortion obvious in LTspice?
With 1–2 V peak‑to‑peak input, LTspice clearly shows the crossover notch. With a large drive, the output can look cleaner but sits lower by roughly one V_BE. Both observations came from a quick LTspice check. [Elektroda, Anonymous, post #21679605]
My 20 mV input shows nothing. Is that expected?
Yes. Tens of millivolts are far below the ~1.2 V peak‑to‑peak threshold of two silicon junctions without bias. Increase input amplitude or add bias before expecting symmetrical swing and gain. [Elektroda, Anonymous, post #21679598]
Which pins go where for the PNP in a b16 V test?
Tie the PNP emitter to the shared emitter node with the NPN. Connect the PNP collector to −6 V. Keep the bases driven together from your source through suitable impedance. That orientation restores proper push‑pull action. [Elektroda, Anonymous, post #21679598]
Quick 3-step: how do I bring this stage to life?
- Fix PNP orientation: emitter to the shared emitter node; collector to the negative rail.
- Set input to ≥1.2 Vp‑p so both devices conduct.
- Add slight bias to keep both transistors just on near 0 V.
[Elektroda, Anonymous, post #21679598]
Why is the output smaller than the input when it does work?
Expect a V_BE drop. With larger drive, the output looks clean but sits lower by roughly one base‑emitter junction. That’s normal for emitter followers and was observed in LTspice on this exact topology. [Elektroda, Anonymous, post #21679605]
What 19s the next improvement after it 19s working?
Design a bias network to eliminate the dead zone and stabilize quiescent current. Proper biasing is the step that turns a rough test stage into a low‑distortion block suitable for audio experiments. [Elektroda, Anonymous, post #21679598]
