FAQ
TL;DR: Set Vg ≈ 0.05 mV and use 1 kHz; “1 kHz is a good signal frequency to use.” Configure sources for VCC/DC, VCM/DC, Vg/SINE, and make Cinf large so it’s near-short at 1 kHz. [Elektroda, Anonymous, post #21684382]
Why it matters: This FAQ helps LTSpice users wire OTA-style test benches correctly and hit target small-signal gain without clipping.
Quick-Facts
- Vcc and Vcm are DC sources; Vg is AC/SINE; Cinf is a coupling cap that shorts at test frequency. [Elektroda, Anonymous, post #21684366]
- Starter values: Vcc = 10 V, Vcm ≈ 0.5·Vcc; keep Vg amplitude < Vcm. [Elektroda, Anonymous, post #21684366]
- For R1 = 15 kΩ and β(Q5) ≈ 500, R2 ≈ 0.97 MΩ yields ~1500× small‑signal gain. [Elektroda, Anonymous, post #21684381]
- Size Cinf so its reactance ≪ 15 kΩ at 1 kHz (i.e., “behaves as a short”). [Elektroda, Anonymous, post #21684379]
- With R2 ≈ 0.97 MΩ, pulldown limit is ~10 µA, so Vout_peak < 0.15 V; keep Vg_peak < 0.1 mV. [Elektroda, Anonymous, post #21684381]
Quick Facts
- Vcc and Vcm are DC sources; Vg is AC/SINE; Cinf is a coupling cap that shorts at test frequency. [Elektroda, Anonymous, post #21684366]
- Starter values: Vcc = 10 V, Vcm ≈ 0.5·Vcc; keep Vg amplitude < Vcm. [Elektroda, Anonymous, post #21684366]
- For R1 = 15 kΩ and β(Q5) ≈ 500, R2 ≈ 0.97 MΩ yields ~1500× small‑signal gain. [Elektroda, Anonymous, post #21684381]
- Size Cinf so its reactance ≪ 15 kΩ at 1 kHz (i.e., “behaves as a short”). [Elektroda, Anonymous, post #21684379]
- With R2 ≈ 0.97 MΩ, pulldown limit is ~10 µA, so Vout_peak < 0.15 V; keep Vg_peak < 0.1 mV. [Elektroda, Anonymous, post #21684381]
What do VCM, Vg, VCC, and Cinf mean in this LTSpice schematic?
VCC is the supply DC source. VCM is a DC common‑mode bias. Vg is the AC (SINE) input source. Cinf is the output coupling capacitor sized to act like a short at your test frequency, isolating DC at the load. [Elektroda, Anonymous, post #21684366]
How should I place the sources in LTSpice to make it simulate?
Use independent voltage sources: one DC source for VCC, one DC source for VCM feeding both transistor bases, and one SINE source for Vg at the input. Ensure polarities match the schematic and reference grounds correctly. “Both inputs to Q1 and Q2 need to be voltage sources.” [Elektroda, Anonymous, post #21684366]
What starter values work for first‑run simulations?
Set VCC = 10 V. Set VCM ≈ VCC/2. Choose Vg as a small SINE. Keep Vg amplitude well below VCM. Pick R1 = 15 kΩ. Then sweep R2 to set quiescent currents and gain. This gets you a clean baseline. [Elektroda, Anonymous, post #21684366]
How big should Cinf be at 1 kHz so it behaves like “infinite C”?
Pick Cinf so its reactance is tiny versus 15 kΩ at 1 kHz. In practice, select C so XC ≤ 1/10 of R1 at 1 kHz to minimize AC loss and DC coupling. “Cinf behaves as a short‑circuit at the frequency of Vg.” [Elektroda, Anonymous, post #21684379]
What Vg settings reduce errors and clipping?
Use 1 kHz and a very small amplitude. A practical pick is Vg_peak ≈ 0.05 mV. This keeps the stage in small-signal operation and avoids saturating current mirrors during bring‑up. “1 kHz is a good signal frequency to use.” [Elektroda, Anonymous, post #21684382]
How do I compute R2 to target Av ≈ 1500 with R1 = 15 kΩ?
With Ic(Q7)=Ic(Q8)≈(VCC−VBE)/R2 and β(Q5)≈500, gm≈40·Ic(Q2). The chain gain gives Av≈gm·β(Q5)·R1. Solving yields R2 ≈ 0.97 MΩ for Av ≈ 1500 at the stated betas and R1. “Vout/Vg = 1500 volts/volt.” [Elektroda, Anonymous, post #21684381]
Why do I see a flat line at the output?
Check that the base inputs are true voltage sources and that Cinf is large enough. Plot Ic(Q1–Q4), Ib(Q5), and Ic(Q5) versus time. If currents are flat, your sources or biasing are miswired or Vg is too small to observe. [Elektroda, Anonymous, post #21684387]
What limits my maximum undistorted output with R2 ≈ 0.97 MΩ?
Pulldown is limited by Q8’s current, about 10 µA. That caps Vout_peak near 0.15 V across 15 kΩ. Keep Vg_peak under ~0.1 mV to avoid clipping. This is the key small‑signal edge case in this topology. [Elektroda, Anonymous, post #21684381]
How do I pick R2 if my transistor Ic_max is known?
Design quiescent Ic to around Ic_max/10 for small‑signal devices. Choose R2 so mirror currents land in the 1–10 mA range unless your load forces lower currents. This sets gm and usable swing before clipping. [Elektroda, Anonymous, post #21684371]
What does “operational transconductance amplifier” (OTA) imply here?
It behaves like an OTA core: input voltage modulates transconductance, producing an output current into the load. You can lower R2 to boost current headroom, then control closed‑loop gain with added resistors and capacitors. [Elektroda, Anonymous, post #21684376]
Can I stabilize and set gain without huge R2 sensitivity?
Yes. Reduce R2 to raise bias currents and add two resistors and two capacitors to establish closed‑loop gain and bandwidth. This prevents current‑limit clipping while meeting target Av in practice. [Elektroda, Anonymous, post #21684385]
Do LTSpice units differ from SPICE?
No. LTSpice uses standard SPICE units and models. You can export a classic SPICE netlist. “They’re mostly running a standard SPICE engine under the graphical interface.” [Elektroda, Anonymous, post #21684383]
What frequency should I test at if I only need a quick check?
Use 1 kHz. It is high enough for quick time‑domain observation and low enough for manageable capacitor sizes. “1 kHz is a good signal frequency to use.” [Elektroda, Anonymous, post #21684382]
Quick 3‑step: How do I verify small‑signal gain in LTSpice?
- Set VCC=10 V, VCM=5 V, Vg=SINE(0 50µV 1k).
- Choose Cinf so XC≪15 kΩ at 1 kHz; set R2≈0.97 MΩ.
- Run .tran; plot V(out)/Vg and Ic(Q2), Ib(Q5), Ic(Q5) to confirm ≈1500× and linearity. [Elektroda, Anonymous, post #21684381]
