FAQ
TL;DR: Need multiple kHz–MHz signals from one reference? DDS chips reach up to 100s of MHz; “PLLs would certainly do the job.” [Elektroda, Anonymous, post #21680229]
Why it matters: This FAQ shows builders how to fan out one stable reference into many simultaneous, tunable outputs with practical part choices and traps to avoid.
Quick-Facts
- DDS can generate sine waves digitally via a lookup table and DAC; modern units span to 100s of MHz. [Elektroda, Anonymous, post #21680229]
- AD9106 is a four‑channel DDS option with demo boards for evaluation. [Elektroda, Anonymous, post #21680229]
- CD4059 divides by 3–15999; 74HC4059 accepts ≈18 MHz max at 5 V. [Elektroda, Anonymous, post #21680233]
- Separate VCOs are typically required unless outputs are integer‑related; AGC helps level amplitude. [Elektroda, Anonymous, post #21680231]
- Crystal‑plus‑divider “hybrid” works; filter or op‑amp shaping turns squares into sines. [Elektroda, Anonymous, post #21680232]
Quick Facts
- DDS can generate sine waves digitally via a lookup table and DAC; modern units span to 100s of MHz. [Elektroda, Anonymous, post #21680229]
- AD9106 is a four‑channel DDS option with demo boards for evaluation. [Elektroda, Anonymous, post #21680229]
- CD4059 divides by 3–15999; 74HC4059 accepts ≈18 MHz max at 5 V. [Elektroda, Anonymous, post #21680233]
- Separate VCOs are typically required unless outputs are integer‑related; AGC helps level amplitude. [Elektroda, Anonymous, post #21680231]
- Crystal‑plus‑divider “hybrid” works; filter or op‑amp shaping turns squares into sines. [Elektroda, Anonymous, post #21680232]
Can I use PLLs to create many simultaneous frequencies from one reference?
Yes. Use one PLL per independent frequency when outputs are not simple integer multiples. Share a common reference clock and a controller to program each loop. The VCO in each loop sets its band; wide tuning ranges are harder to stabilize. Plan loop bandwidth and filtering per channel. [Elektroda, Anonymous, post #21680231]
Do I always need a separate PLL/VCO for every output?
Not if the outputs are integer‑related. You can synthesize one high‑frequency source and divide it down to multiple channels. Otherwise, independent tuning requires separate VCOs and loops. Share the programming interface and master clock to reduce duplication. [Elektroda, Anonymous, post #21680231]
Is DDS better than PLL for multi‑channel generators?
DDS is often simpler for many channels. It creates sine waves digitally from a table and DAC, and modern parts cover up to the 100s of MHz. Multi‑channel DDS ICs such as AD9106 reduce part count. “They are used in many modern signal generators.” [Elektroda, Anonymous, post #21680229]
How can I stay (mostly) analog yet keep things simple?
Use a crystal or stable oscillator at or above your highest frequency, then add programmable dividers for each channel. Shape the square outputs into sines with filters or op‑amp stages. This “hybrid” keeps a single reference and analog outputs while avoiding many VCOs. [Elektroda, Anonymous, post #21680232]
What is a VCO, and what’s the catch?
A VCO is a voltage‑controlled oscillator used inside PLLs. It tunes frequency with a control voltage. Wide tuning ranges complicate design and degrade performance. Use amplitude leveling (AGC) if you need constant output level across the band. [Elektroda, Anonymous, post #21680231]
What is a rate multiplier, and when would I use one?
A rate multiplier outputs a fractional multiple of its input clock (e.g., N·Fin/16 for binary types). Devices like the CD4089 let you set N via pins, enabling flexible frequency steps derived from one high‑frequency clock. [Elektroda, Anonymous, post #21680233]
What do CD4059 and 74HC4059 do in this context?
They are programmable divide‑by‑N counters. CD4059 divides by 3–15999. 74HC4059 is the faster CMOS variant and takes about 18 MHz at 5 V. Use them to derive many exact frequencies from one high‑frequency source. [Elektroda, Anonymous, post #21680233]
How do I avoid a floating selector pin in my divider bank?
Add a pull‑up or pull‑down to the control pin so an unselected switch doesn’t leave it floating. A 100 kΩ resistor to VDD or ground on the first position prevents undefined states and glitches on startup. [Elektroda, Anonymous, post #21680236]
Can I get a sine wave without a DAC?
Yes. Clock a shift register with a pattern of ones and zeros, sum outputs through a resistor ladder, and filter. Equal resistors yield a triangle; tailored values approximate a stepped sine that smooths to a clean sine after RC filtering. [Elektroda, Anonymous, post #21680235]
How do I build a simple multi‑output generator from one crystal?
- Choose a crystal above your highest target frequency.
- Feed programmable dividers to create each channel frequency.
- Low‑pass filter or op‑amp‑shape each output into a sine as needed.
This scales well when outputs are integer‑related. [Elektroda, Anonymous, post #21680232]
Do I need sine or square outputs for my application?
Define your load and purity requirements first. Square waves are easy after division. Sine outputs need filtering or a DDS/DAC path. If you need constant amplitude or low spurs, budget for leveling and proper filters. Ask yourself what spectral purity you need. [Elektroda, Anonymous, post #21680231]
What performance should I expect from DDS?
DDS purity depends on DAC resolution, clock quality, and output filtering. Many lab generators use DDS because it’s stable and wideband. Start with a clean reference, then filter adequately. “Sine waves are synthesized using a lookup table and DAC.” [Elektroda, Anonymous, post #21680229]
