Repeated IX3180G Optocoupler Failure in PWM Circuit at 97kHz—What Could Be Wrong?

I've built and tested a very simple PWM that drives either a Peltier heat pump or a heater. Circuit appears to work quite well either way. I laid out a PCB and after some tens of hours of operation the IX3180G optocoupler failed. This has occurred multiple times now. Consulted with the chip manufacturer and implemented his recommendations to no avail. The part fails after some tens of hours of operation. I am using a conservative 4 layer PCB, very short traces, etc. The switching frequency is 97 Khz. D2/R4 are present strictly to protect the optocoupler. Tearing my hair out...

Hi, Richard,

Do you know which side of the optocoupler is failing? Do you have an oscilloscope you can check the voltages appearing across components with? Make sure there are no voltage transients due to switching that are stressing the part by exceeding the optocoupler's maximum voltage ratings. Are any of the other components being damaged when the optocoupler fails?

Best,
JD

The opto is normally partially conducting after it fails so I presume that means the output side is failing. That puts the mosfet partially on, dragging the power supply down. The heatsink is conservative so no other components are typically damaged.

Changing out the opto, which is now running hot, normally restores proper operation. So obviously it's the opto that's failing. But I can't find the source of the failure.

Checking with a proper scope is not an option in my case. All I have is a poor man's USB-based scope card. It tends to show noise pretty much everywhere I look which I'm sure is not the case.

The latest failure hampers my investigation however as D1 has shorted and damaged the board. So I'll need a few days to build and test a new board. I can try to capture some waveforms then.

Put resistors in series with output pins 6 and 7 of the optocoupler, with the junction of the two resistors driving the existing gate resistor, so there is resistance between pins 6 and 7 of the optocoupler. The added resistors prevent optocoupler burnout when the optocoupler's two MOSFETs are transiently on simultaneously as the optocoupler switches.

You are not using the isolation feature of the optocoupler, so you might be able to use a level-shifting gate instead.

Definitely not an expert here, but are you sure that your input side ("PWM") can safely sink 12mA @ 12V? I ask only because driving your opto directly from many low-voltage microcontrollers can't handle either that current or voltage level. I do realize that you said that replacing the opto causes the circuit to work again for some period of time, but that's the only thing that I can see that might be an issue.

Also, have you measured the current through your current-limiting resistor to confirm that the current through the LED is the ~12mA that you're expecting (because a wayward 100ohm resistor would certainly not be your friend here)?

The only other reach would be to eliminate the opto and drive the pin 6/7 trace directly with 0.5V and 12V steady to ensure that everything else holds up.

These are all tests that can be done with just a voltmeter, if your lack of instrumentation is a constraint. Just for "fun" you could also doing something like putting another discrete IR LED and (same) resistor between pin2 and GND to see if you fry that also. You'll be able to see whether it's still working through the viewfinder of a digicam or cameraphone which will show you the IR.

Otherwise... perplexing!





-e

Can't try Peter's idea as pings 6 and 7 are internally wired together. I am using the isolation feature by driving the input with an open collector over several feet of wire, to avoid ground shift worries.

Input side is thoroughly tested, driven by a conservatively rated open collector and 12mA current is verified.

No detectable heat buildup anywhere during normal operation. The MOSFET has a conservative heatsink so it runs cool.

Only other clue is that D1 has fried twice. Can't see a reason for this either but I'm subbing in a more conservative part.

I ran the design through the IXYS support engineer and he finds no problem. Yet after many hours of operation the opto dies regularly. Switching manufacturers in a desperate attempt to cure it.

Dear Richard,

I am trying to figure out how the output side of this circuit is supposed to work. When driving a TE cell, you want to minimize current ripple because spikes in current cause losses in the resistance of the cell as a function of the square of the peaks of those spikes, making the cell less efficient for cooling (has more internally generated heat to deal with).

Thinking "out loud" here... let's see... Yikes! Q2 is an 80 A MOSFET! How big a TE device are you driving? Oh, I see, this is a buck converter with the switching on the negative side of the voltage source. The duty cycle determines the voltage that will appear across C4, ranging from about 0 to 13 V as duty cycle ranges from 0 to 100 %.

You do realize that the common-mode voltage of your PDRV output terminals will vary from 0 to 13 V at your switching frequency, yes? The PRDV terminals are only connected to the TE cell or resistive heater, right? No additional tie to GND? (It is unfortunate that your schematic for Q2 does not also show it's body diode, although I don't think it ever commutates on during operation of this circuit because there is nothing to push the voltage of PDRV- below GND.) This common-mode voltage is why your output voltage waveforms have so much "noise" on them. That is not noise. It is real. You need to read them differentially to see the voltage appearing across them. Shy of a true differential probe or isolated probe, you could take the difference between them by referencing two scope probes to GND and taking the difference in software. Don't know if your USB scope can do that, or if it is fast enough for 97 kHz switching.

D1 is a key part of the buck regulator. When Q2 is on, it pulls PDRV- down to GND. PDRV+ follows suit, albeit at whatever voltage is across C4 at the time. This causes current to build in L1 and voltage to rise across C4 and the load. When Q2 turns off, the current in L1 continues to flow down through C4 and the load then finds its way back up through D1 and to L1. This causes current to decrease and the voltage across C4 and the load to fall. Note that when this is happening, the voltage of PDRV+ is higher than 13 V by whatever the voltage is across the load and C4 at the time. Which means that that voltage also appears across Q2. But Q2 is rated for 40 V so it should be good with the 26 V (plus diode drop) it might see.

Now, I see that D1 is a Silicon Carbide Schottky rated at 600 V, 24 A. We must be careful here to note that the current flowing through the load is the average of the current flowing through L1. But peaks of L1 current flow through C4. All that current flows through Q2 when Q2 is on, none of it through D1. But when Q2 is off, all the current through L1 also flows through D1. Depending on the duty cycle, the average D1 current can be quite small or it can be nearly equal to the load current. The peaks of the current ripple will be higher than the ripple midpoint or average load current.

Do you know how much current you are driving through your load? You need to make sure you are not over driving D1. Remember it carries all the load current (and then some peaks through C4) for part of each switching cycle.

Regarding isolation. I think Peter's point is that since you are powering both the input and output sides of the opto from 13.0V and you are referencing the input of the opto to GND, you are not getting any isolation between input and output. To achieve isolation, the input should be powered from a separate power supply on the other end of your several feet of wire and with no connection between input and GND. One advantage of the opto is that it provides a stiff drive for the Gate of Q2. If you got rid of it you would still need a robust gate driver chip.

A scope would really help here. I've not used a poor-man's USB scope so I don't know how limited they are.
But I would think that referencing the scope probe to GND and probing any pin on the opto should give you a better insight into what is happening to the opto. And you should be able to see the output of Q2 (PDRV-) as well. You have to make sure your PC and USB GND and your circuit's GND are all tightly connected to each other and nothing else is connected to GND (no GND loops). Or put A USB isolator in the USB link to separate the PC GND from the setup.

I hope this helps and you can figure this out.

Best,
JD

JD,

Thanks for the input. Your analysis largely mirrors my own.

The spec'ed load current using the TE devices was 19.2A. The PTC ceramic heater current calculates as roughly 18A. The MOSFET was certainly a bit overrated but as it's a one-off design I did not need to tweak costs. Can't see a problem there.

D1 appears to be up to the job but since switching the load to a PTC ceramic heater I've blown it twice. I've ordered a device with a higher current rating but can't see the problem and I doubt it's related to the opto failures. The D1 failures are probably due to spec issues with the heaters. They are low-cost Chinese parts that come with no specs other than the wattage rating. Haven't found any info with which to calculate the temperature/resistance relationship. Hopefully the upgraded diode will do the trick.

The common mode voltage doesn't concern me, I just ran a heavy twisted pair out to the load.

Perhaps I'm not following the isolation discussion properly but I can't see a problem there either. My thinking was that using an opto in this fashion would free me from worrying about ground shifts between the control board and the driver board. Would use of a separate supply somehow improve reliability?

I don't feel closer to understanding the opto failures. Haven't been able to put a scope on it, hope to soon.

Rich

Does your USB scope have an external-trigger input? If so, connect the external-trigger input to PWM and set the sweep to use the external trigger. This will give you stable waveforms.

Use your scope to look across C5: connect ground to GND and input to 13.0V. What is the peak voltage you see in the "noise"? Make the same measurement at the terminals of the 13.0V supply, to see the effect of the inductance of the 13.0V cable. Compare the output voltage rating of the optoisolator to the peak you measured across C5.

Use your scope to measure the "noise" peaks on PDRV+ and on PDRV-.

Use your scope to look at the "noise" between the optoisolator output and GND. Compare the positive peak to the optoisolator rating. Compare the negative peak to zero.

As JD asks, what is the load current? Does the problem occur with the resistive heater load? If so, work with that load until we figure this out. Knowing the resistance of the heater will help us analyze the behavior. What is the time-constant = Rheater * C4? Compare this to the 10.3 microsecond period of 97 kHz.

Standard buck converter would swap L1 and (C4 in parallel with the load), to minimize the alternating common-mode voltage on the output.

Is the inductor really 15 microhenries and not 15 millihenries? Compare the inductor's reactance at 97 kHz to the heater's resistance.

I had to order new boards to replace the dead one. I hope to have scope readings next week.

Nominal load current is about 16A; the nonexistent specs on these heaters make that number a bit dodgy and its quite impractical to measure a PTC ceramic with my gear.

The problem occurred with both loads and the ceramic heater is now the only option. Resistance calculates as 0.72 ohms.

My original intent for C4 was to minimize ripple at the load since TE devices are reputedly poor in handling this. I don't remember what kind of brain fart lead to the decision to use a 2700 uF capacitor as the Texas Instruments buck calculator recommends a minimum of 21 uF. I am switching to 82 uF to minimize ESR. Haven't built this yet. 82uF * 0.72 ohms = 59 uS.

Will also increase C5 from 10uF to 30uF to reduce input ripple.

Yes the inductor is actually 15 uH, which is reasonable according to the TI calculator.

Not clear what you intended by swapping L1 and C4. The load is meant to be driven by a twisted pair across C4. As it's simply a resistive heater I can't imagine that common-mode voltage is a problem. Am I missing something?

Rich

The common-mode voltage makes the heater and its cable act as an antenna, and the emitted noise spikes might be getting into your circuits. Try listening with an AM radio tuned between stations.

15uH is a reasonable inductance for your inductor, as the inductive_reactance = 2 * pi * frequency * inductance = 9 ohms at 97 kHz, is large compared to your load resistance. This makes the AC current through the inductor small compared to the DC current through the inductor, which is correct operation. The inductor absorbs the voltage difference between 13 volts and the voltage across the load.

Measure the heater's cold resistance: Connect a 1000-ohm resistor in series with the heater to your 13-volt supply, and measure the voltage Vmeas across the heater. The 1000-ohm resistor puts 13mA = 13V / 1000ohms through the heater, so Ohm's Law will let you calculate the resistance of the heater: Rheater = Vmeas / 13mA. The heater has a positive temperature coefficient, so the cold resistance is lower than the hot resistance. The PWM circuit must safely provide enough output current to drive the cold resistance.

What are you using for your 13-volt supply? How long is the cable from the supply? What is the series inductance of the cable?

D2 1N5819 protects the optoisolator output (pins 6 and 7) from transients going negative with respect to ground. I suggest adding D3 1N5819 from the optoisolator output to the 13-volt supply, to protect the optoisolator output from transients going more positive than the supply. The 1N5819 is a Schottky diode, which has a lower forward voltage than silicon diodes have, so keeps the parasitic source-to-drain silicon diodes in MOSFETs from conducting.

Get a 12-volt 12-watt incandescent lightbulb, such as are (or were) used in high-intensity lamps and in automotive tail lights. When you get your new board running, first run with that lightbulb as a load, and see if the board is reliable and runs cold with that load. You can verify visually that varying the PWM duty cycle varies the brightness of the lightbulb.

The optoisolator has output pins 6 and 7 connected together internally. This implies that the optoisolator is designed so that the two output MOSFETs are never both on at once.

Digi-Key reports that the IX3180G has been obsoleted by manufacturer IXYS. Datasheet says the IX3180G is rated for output-side supply 10 V to 20 V, so the 13 V supply should be OK.

Your problem may be due to details of your PCB layout, giving transient voltage spikes between different places of GND.

Ceramic heaters actually exhibit a small negative temperature coefficient across the lower operating range, curving sharply upwards near the design temperature. I have arranged four 200W heaters in a series-parallel arrangement that gives me 200W effective power while avoiding the extreme temperatures which I do not require. As I do not approach the design temperature I expect lower current at room temperature. To validate my thinking I followed your advice. A 200W/12V rated heater produces a calculated resistance of 0.72 ohms. I measured 0.98 ohms hot and 1.05 ohms at room temperature. Allowing for some connection resistance this agrees with the theory. Both readings are well within tolerance.

The 13-volt supply is a Meanwell LRS-350-12. An economy line-operated 350W switcher but it appears to be well behaved. Why 13V? I tweaked the pot to optimize performance of the old Peltier system. The power supply cable is about 2 feet long, an 18AWG twisted pair. I don't have the gear to measure inductance but I can't imagine it's significant. When I get the new board installed I'll beef up the wiring just to be sure.

The addition of D3 is a good suggestion. I will add that to the next spin of the board which unfortunately will not happen for a couple of weeks.

I'm aware of the obsolescence so I've bought enough parts from ON Semiconductor to keep me stocked.

I've laid out what I believe to be a conservative 4-layer design. I have even placed a component side ground plane around the opto and related components. I can't imagine how to improve this.

Still don't have a functioning board yet so no scope pics yet.

The opto will run warm. Every cycle of the 97kHz, Q2 is turned on and then turned off. Q2's gate needs Qg=0.1uC (uC = microcoulombs) of charge to change the gate voltage from 0V to 13V to turn Q2 on. This charge must be removed to turn Q2 off. Eg = Qg * 13V = 1.3 uJ (uJ = microjoules) is the energy drawn from the 13V supply to turn on Q2 for each cycle of the 97kHz. Half of this energy is disspated in the opto when the opto turns Q2 on, and the other half is disspated in the opto when the opto turns Q2 off.

Eg * 97kHz = 126mW is the power dissipated in the opto due to driving Q2's gate. Adding the opto's 40mW dissipation due to the opto's supply current, we get 166mW dissipation in the opto. The opto's temperature is rated to rise 1 degree C for each 7.5mW of dissipation. Divide 7.5 mW/degC into 166mW to get 22degC=40degF temperature rise in the opto.

Though it's been a while your opto power calcs sound like my own. Also checked by the engineer at IXYS. It's within normal range and the circuit operates at roughly room temperature so temperature rise is well below the problem range.

The new boards are due in soon and I will try to get some scope pics. It will need a lot of run time to see whether it fails again.

Thanks.

I have made some progress.

I replaced D1 with a device that has a much lower Vf and gave it better heatsinking. It seems to be behaving now.

I purchased a low-end Picoscope and after a brief evaluation it's far better than my old scope. Seems surprisingly good for a cheap USB scope.

The scope yielded a big surprise. I've been barking up the wrong tree. The load transient created by the PWM were far too much for the SMPS. The output turned into a sin wave that peaked at around 20V. Ouch, did not expect that. I have looked around for something to read to help me better understand SMPS transient response with little luck so far. Ideas would be appreciated.

As a workaround I added 230uF MLC caps from +13V to gnd. Max output is now 13.5V. I imagine that could solve the opto failure problem. But I'm not comfortable with putting such a high capacitance load on the SMPS. Do guidelines exist for max capacitance on a SMPS?

The opto's maximum-recommended Vcc-Vee is 20V, and absolute-maximum Vcc-Vee is 25V from the datasheet, so the SMPS transients may well be what was blowing the opto.

If you have a spare 15uH inductor like L1, you could put a 15uH inductor in series between the SMPS and the 230uF MLC caps, to isolate the SMPS from the caps. What is L1's series DC resistance, and hence DC voltage drop at your load current? What frequency does the SMPS run at?

Hi, Richard. Nice to know you found a cheap USB scope that is surprisingly good. Care to shar which scope you bought? I am also glad you now have a tool to reveal the secrets of your circuit!

A lower Vf drop on D1 would certainly help reduce power dissipated in that diode. Care to share the part number of the new diode?

I am not a SMPS expert by any means but I do know that these circuits work by momentarily storing some energy kinetically as current flowing through the inductor then converting that energy back to potential energy stored in a capacitor. Thus by switching the inductor (L1 in your circuit) across the input capacitor (C5), current builds in Ll while voltage falls in C5 until L1 is then switched across C4 through D1. At that point the current decreases and the energy is transferred to C4 with a corresponding increase in voltage of C4. Thus the voltage of C5 and C4 can be quite different. The voltage across the intermediary, L1, adjusts instantaneously as needed to cause current through the respective capacitors.

With this in mind, I would think that the size of C5 and C4 do not matter. They will affect response time of the circuit, but I do not think they would over-stress the SMPS in any way. They will certainly keep ripple voltage (switching spikes) down which is a good thing. Thus, I say, if you have the board space, increase the capacitance.

Now that I think about it, using a 10 uF capacitor (C5) as the source for supplying energy to a 2700 uF capacitor (C4) is woefully inadequate. The output capacitance of your 13.5 V supply must be what is doing most of the work so adding a 230 uF cap to C5 seems very wise otherwise 13.5 V will vary all over the place. I would probably go even higher.

Perhaps an SMPS expert can add to or correct my assertions here.

Best,
JD

Hi JD,

I picked up a Picoscope 2000 series. Considering that it's dirt cheap, it's pretty good. Much more stable than my previous one. It's just a basic low-frequency job but it gets the job done for me.

I switched the diode to MBRF2045 and made use of the insulated tab to share a large heatsink with the MOSFET. Seems to work well now.

C4 has already been reduced from 2700 uF to 82. Don't need terribly low ripple to please a heater.

I will lay out a new board with much large bulk capacitance to keep the power supply ripple in hand. Been running for a couple of days now without failure.

Rich

Peter,

L1 spec says 0.0025 ohms max. So voltage drop would be roughly 0.0225 * 16 = 0.040 V. Not much. Can't find a frequency spec for the SMPS. Is that something I can measure given that my low end scope shows noise everywhere?

Any experience with MOSFET ringing? I am seeing quite a bit of ringing at both gate and drain at each transition. I have read an app note from Toshiba on the subject and the recommendations for mitigation are rather difficult to implement. They recommend more gate resistance, which I can increase to see if it helps. They recommend a small inductor in the gate as well. Not much I can do about stray inductance, it seems.

The MOSFET was chosen for low cost and low Rds. It's current rating is higher than I require. Would it help to choose a device with a lower Ciss? The tradeoff would be a bit more Rds but I think I can manage that.

Rich