LNA Output Always Negative in gdpk45 NMOS Design at 2.4GHz—Schematic Check?

doduyhoangpennyduy wrote:

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@ElektrodaBot I barely design this LNA but it doesnt work. I have problem with the output. The test result is always in the negative range.
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Initial assessment of available information
You built a single‑NMOS common‑source LNA in gpdk45 for 2.4 GHz with:
- Gate: RF from Port0 (50 Ω) → 10 pF series C → 80 nH series L → gate. Gate DC bias via 200 kΩ to 0.65 V.
- Source: 100 pH inductor to ground.
- Drain: to VDD = 1.2 V through 150 Ω; AC‑coupled to Port1 (50 Ω) via 10 pF.
- Observation: “output is always in the negative range.”

At 2.4 GHz this network is not a matched RF LNA; component values force severe signal blocking at the input and provide a lossy, non‑resonant output load. The “negative” result most likely means either S21 < 0 dB (attenuation), or simply the expected 180° phase inversion of a common‑source stage in time domain.

Direct answer to the question
Your LNA does not work at 2.4 GHz because:
- The 80 nH series gate inductor presents ≈ j1200 Ω at 2.4 GHz and effectively blocks the RF from reaching the gate.
- The 100 pH source inductor is ≈ j1.5 Ω at 2.4 GHz and provides essentially no inductive degeneration for 50 Ω input matching.
- The 150 Ω drain resistor is a poor RF load at 2.4 GHz, wastes headroom, and with a simple 10 pF coupling capacitor gives no output resonance or matching to 50 Ω.

Replace the gate and source inductors with realistic nH‑range values and use an inductive/tuned load at the drain. Then design proper input and output matches.

Detailed problem analysis
1) Input path (Port0 → C_series 10 pF → Lg 80 nH → gate)
- Reactances at 2.4 GHz:
- X_L(80 nH) ≈ +j1206 Ω
- X_C(10 pF) ≈ −j6.6 Ω
- Consequence: the 80 nH dominates; the source sees ~1.2 kΩ in series. Almost all incident power is reflected (S11 ≈ 0 dB), so S21 appears “negative”.

2) Source degeneration (Ls = 100 pH)
- X_L(100 pH) ≈ +j1.5 Ω at 2.4 GHz.
- In an inductively degenerated CS LNA the source inductance sets the real part of Zin and helps the 50 Ω match. 1.5 Ω is far too small; typical Ls is in the few‑hundred‑pH to low‑nH range, depending on gm and Cgs.

3) Drain/output network (Rd = 150 Ω, C_cpl = 10 pF to Port1 = 50 Ω)
- X_C(10 pF) ≈ −j6.6 Ω, so the output is just AC‑coupled into a 50 Ω load with no impedance transformation.
- With a 150 Ω resistive load to VDD, small‑signal gain magnitude is roughly |Av| ≈ gm·(Rd || 50 Ω || ro). That is limited, and the lack of a resonant Ld–Cd tank at 2.4 GHz removes the gain “boost” you expect from an RF LNA.
- Headroom: with a few mA drain current, the 150 Ω drop eats 0.3…0.8 V from 1.2 V supply, pushing VDS close to the edge and reducing gain and linearity.

4) What “negative” might mean
- Time domain: A common‑source inverts phase; negative swing is normal.
- S21 in dB: If your S‑parameter analysis shows S21 < 0 dB at 2.4 GHz, that’s attenuation due to the input being blocked and the output being unmatched.
- Output power in dBm: Small‑signal output power being negative dBm is not by itself problematic; compare input and output to get gain.

Current information and trends
- 2.4 GHz CMOS LNAs almost universally use: common‑source with inductive source degeneration; often a cascode for isolation; Lg/Ls for input match; a high‑Q Ld–Cd resonant load; and a simple L/C output match to 50 Ω. Resistive RF loads are avoided due to noise and gain penalties.
- On‑chip inductors at 2.4 GHz are typically 0.3–5 nH with Q ~ 8–20. Values like 80 nH are off‑chip/bond‑wire scale and impractical on silicon; at that value, SRF and parasitics would dominate.

Supporting explanations and details
- Gate path design: Choose Lg to resonate the net input capacitance (≈ Cgs + Cpad + part of Cgd) at 2.4 GHz, after accounting for Ls. The condition Imag{Zin} ≈ 0 near f0 gives Lg ≈ 1/(ω0^2·Cgs_eff) − Ls. That places Lg in low‑nH for realistic Cgs_eff (hundreds of fF to a couple pF).
- Real part for 50 Ω: Increase Ls until Re{Zin} ≈ 50 Ω at f0. In practice you sweep Ls and watch S11; gm and Cgs at the chosen bias determine the exact Ls needed.
- Output load: Use an Ld from drain to VDD as an RF choke and to form a parallel resonance with the drain capacitance (Cgd/Cdb/Cwire). Pick Ld ~ 1–5 nH, then compute Cd so f0 = 1/(2π√(Ld·Cd)) ≈ 2.4 GHz. Follow with a simple L‑match or just set the coupling capacitor and a shunt C/L to transform the tank impedance to 50 Ω.
- Biasing: Keep the drain near mid‑supply for swing and saturation. An inductive load preserves DC headroom (no DC drop). Your 200 kΩ gate bias is fine for RF isolation; ensure the bias node is well decoupled to ground at RF.

Practical guidelines
Start with a minimal, working RF topology:
- Input
- Ls: 0.3–1.0 nH (initial guess).
- Lg: 1–5 nH (tuned so Imag{Zin} ≈ 0 at 2.4 GHz).
- Keep the 10 pF series cap only if you need DC block; at 2.4 GHz 10 pF is large. 200–1000 fF is often sufficient and occupies far less area on silicon.
- Transistor
- Use minimum L; choose W and bias for gm in the 20–60 mS range at your power budget. Multi‑finger layout is essential to keep gate resistance low.
- Drain/output
- Replace 150 Ω with Ld ≈ 2–4 nH to VDD.
- Tune Cd so Ld//Cd resonates at 2.4 GHz (Cd is the sum of explicit cap plus parasitics).
- AC‑couple to Port1 with a modest C (e.g., 300–800 fF) and add a shunt C or series L as needed to achieve S22 < −10 dB.
- Decoupling and stability
- Add supply decoupling close to the device (e.g., 100 pF || 1 nF MIM) and an RF choke/isolation resistor in the VDD feed if needed.
- Verify broadband stability (K‑factor/μ‑factor) from, say, 100 MHz to 20 GHz. Add small gate/drain series resistors (2–10 Ω) if required.

Suggested simulation flow (Spectre/ADS, etc.)
1) OP analysis: confirm ID, gm, VGS, VDS; ensure saturation.
2) Small‑signal AC with an ideal high‑impedance load: verify that adding Ld–Cd creates a gain peak near 2.4 GHz.
3) S‑parameter with 50 Ω Ports at both ends: sweep 1–6 GHz, optimize Lg and Ls for S11 < −10 dB, then match the output for S22 < −10 dB. Target S21 ~ 10–20 dB initially.
4) Noise analysis: check NF; adjust bias (gm/Id) and device size to optimize NF while preserving match.
5) Transient/power compression (optional): verify linearity and 1 dB compression.

Possible disclaimers or additional notes
- The exact L/C values depend on your device Cgs/Cgd at the chosen bias and on layout parasitics. After schematic‑level tuning, you must re‑tune post‑layout with extraction.
- If supply headroom is tight at 1.2 V and you consider a cascode, budget VDS for both devices carefully; otherwise stay single‑ended CS.

Suggestions for further research
- Look up textbook CS LNA with inductive source degeneration and drain peaking, and application notes on 2.4 GHz CMOS LNAs. Focus on input match synthesis (Lg/Ls/Cgs) and output tank/match design.
- Practice with a gm/Cgs‑based sizing flow: pick gm from NF and gain, then adjust W to obtain the corresponding Cgs that yields a realizable Lg.

Brief summary
- 80 nH at the gate and 100 pH at the source are the primary reasons your LNA shows “negative” results. They block the input and fail to provide a 50 Ω match.
- The 150 Ω drain resistor produces low RF load impedance and wastes headroom; replace with an inductive load and a tuned/matched output.
- Re‑design with Lg, Ls, and Ld in the 0.3–5 nH range, add a drain tank, and perform proper S‑parameter optimization at 2.4 GHz.

Questions for the user
1) By “negative range,” do you mean S21 < 0 dB at 2.4 GHz, or a negative time‑domain voltage (phase inversion), or negative dBm output power?
2) What are your transistor dimensions (W, L, number of fingers) and the OP results (ID, gm, VGS, VDS)?
3) Which simulator/analysis are you using (S‑parameters/AC/transient), and what are S11/S21/S22 around 2.4 GHz?
4) Are these ideal L/C or PDK inductors/caps? If PDK, what are the Q and SRF of the inductors you used?

Topic: 4160445 (date: January 10, 2026).