Two stage opamp design steps for 5000V/V gain, 10MHz UGB, 30V/us slew, 180nm, PMOS input

hi..all......
iam going to a project on designing of two stage opamp with the following specifications:
1.Gain>5000v/v
2.Unity gain band width=10MHz
3.Slew rate=30v/us
4.Phase margin=60 deg
5.load CL=10pF
6.ICMR=3V

iam like to use PMOS transistors as input transistors...
please give the basic steps how and from where to start my project..iam using 180nm technology

Dear friend,
Hi,
It's so easy , i would like to introduce several references that pretty useful for designing the OTAs
1-CMOS Analog Circuit Design - Allen and Holberg-second edition - page 269 - a design procedure is proposed in this book , i suggest you this book.
2-Design of Analog CMOS Integrated Circuits (behzad Razavi),chapter 9-page 291 , this is my favorite book
3-CMOS Circuit Design, Layout, and Simulation Third Edition by R.J. Baker- chapter 26
also , i send you an article that proposed a design procedure for designing a two-stage OTA,

you can start your design from the Slew Rate parameter (SR=I tail / C load in telescopic and folded cascode topologies and SR=I/C compensation in the two stage topology ) and the GBW requirement afterward.
Good luck with your work, Mohammad

thank you so much..

Hi First go through your spec
I mean with respectoo spec cal the cap and finger the gate and let start layout .