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Logic gate circuit for 3 inputs (A, B, C) with custom output truth table

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Best answers

How can I implement this 3-input truth table with logic gates, and can it be done using only two XOR gates or a single on/off switch?

You can implement the truth table with a single 4:1 multiplexer: use B and C as the select lines, and wire the data inputs as A, not A, not A, and 0 [#21664638] A Karnaugh-map reduction gives the sum-of-products form y = A'B'C + A'BC' + AB'C', which corresponds to 2 NOT gates, 2 AND gates, and 1 OR gate [#21664642] Two XOR gates alone will not work, because the XOR-style approach makes 111 come out as 1, but your table requires 0 [#21664649] The MUX solution is the cleanest and uses the fewest chips/wiring [#21664649] If the toggle switch is meant as a clock or input source, that role is still unclear from the table; the logic function itself is best handled by the MUX or the reduced gate network [#21664649]
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  • #1 21664637
    elsie li
    Anonymous  
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  • #2 21664638
    Satyanarayana Murthy Kara
    Anonymous  
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  • #3 21664639
    Earl Albin
    Anonymous  
  • #4 21664640
    Earl Albin
    Anonymous  
  • #5 21664641
    elsie li
    Anonymous  
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  • #6 21664642
    Syed Shadab
    Anonymous  
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  • #7 21664643
    Mark Harrington
    Anonymous  
  • #8 21664644
    Earl Albin
    Anonymous  
  • #9 21664645
    Earl Albin
    Anonymous  
  • #10 21664646
    elsie li
    Anonymous  
  • #11 21664647
    Mark Harrington
    Anonymous  
  • #12 21664648
    Mark Harrington
    Anonymous  
  • #13 21664649
    Bob Loy
    Anonymous  
  • #14 21664650
    Syed Shadab
    Anonymous  
  • #15 21664651
    Mark Harrington
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  • #16 21664652
    Mark Harrington
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  • #17 21664653
    Bob Loy
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  • #18 21664654
    Mark Harrington
    Anonymous  

Topic summary

✨ The discussion focuses on designing a logic gate circuit with three inputs (A, B, C) to produce a custom output truth table. The output is 1 for inputs 001, 010, and 100, and 0 otherwise. Initial suggestions include using Karnaugh maps for simplification, resulting in a minimized Boolean expression requiring two NOT gates, two AND gates, and one OR gate. A 4-to-1 multiplexer (MUX) controlled by inputs B and C with inputs A, NOT A, NOT A, and 0 is proposed as an efficient hardware solution with minimal chip count and wiring. Attempts to implement the function using only two XOR gates are deemed insufficient due to incorrect output for input 111. The role of a single toggle switch is unclear; it might serve as a clock input for a binary counter to cycle through states, which can then be decoded by the logic circuit. Suggestions include using microcontroller-based programmable logic for flexibility and software simulators like LogicCircuit for design and testing, though Mac compatibility is uncertain. The conversation also touches on practical aspects such as salvaging components from discarded electronics and the evolution from discrete logic to programmable devices like FPGAs and microcontrollers.
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FAQ

TL;DR: For the 3‑input truth table (8 rows), the minimal solutions are either one 4:1 MUX or a 5‑gate discrete design. “Multiplexors (aka Data Selectors) are powerful!” [Elektroda, Bob Loy, post #21664649]

Why it matters: This FAQ helps students and hobbyists choose the simplest, most reliable way to implement the specified logic with A, B, and C.

Quick Facts

What logic function matches this truth table?

A minimized expression is y = A + A̅·B·C̅. This implements the rows 001, 010, and 100 as 1, and all others as 0. It uses two inverters for A and C, two AND gates to build A̅·B·C̅, and one OR gate to combine with A. [Elektroda, Syed Shadab, post #21664642]

Can I build it with only two XOR gates?

No. Two XORs output 1 for A=B=C=1, but the table requires 0. This edge case breaks the XOR‑only idea. “Two XOR gates may not work.” Use the MUX or minimized SOP instead. [Elektroda, Bob Loy, post #21664649]

What’s the lowest chip‑count way to implement it?

Use one 4:1 multiplexer. Tie the select lines to B and C. Feed data inputs as D0=A, D1=A̅, D2=A̅, D3=0. This maps the rows to the required outputs with minimal wiring and one package. [Elektroda, Satyanarayana Murthy Kara, post #21664638]

How do I minimize it with a Karnaugh map?

Three steps: 1) Plot 1s at 001, 010, 100. 2) Group cells to cover those minterms with largest implicants. 3) Read groups to get y = A + A̅·B·C̅. K‑maps quickly show minimal terms for three inputs. [Elektroda, Earl Albin, post #21664639]

How many discrete gates do I need for the SOP build?

Five total: 2 NOT gates (invert A and C), 2 AND gates (build A̅·B·C̅), and 1 OR gate to produce y. This is compact and easy to wire on a breadboard. [Elektroda, Syed Shadab, post #21664642]

Do I need an OR gate after the AND terms?

Yes. Sum‑of‑products requires an OR stage to combine product terms into the final output. Use a 3‑input OR if you expand terms, or 2‑input OR for the minimized form shown. [Elektroda, Earl Albin, post #21664640]

How could a single toggle switch be used here?

Use it as a clock. Drive a 3‑bit counter through 0–7, then decode with a MUX or minimized logic to show the output for each state. The switch alone can’t replace three independent inputs. [Elektroda, Mark Harrington, post #21664651]

Why might a microcontroller be a better choice?

A small MCU can implement the truth table as a lookup with three GPIOs, reducing parts and enabling quick changes. One chip replaces multiple gates, improving reuse and flexibility. [Elektroda, Mark Harrington, post #21664643]

Is the 4:1 MUX approach really that good?

Yes. It yields low wiring and a single IC. As one expert said, “Multiplexors (aka Data Selectors) are powerful!” For this table, the MUX mapping is direct and clean. [Elektroda, Bob Loy, post #21664649]

What Mac software can I use to draw the circuit?

Try LogicCircuit for schematic simulation and learning. The thread notes it and queries Mac availability. If unavailable, use any cross‑platform simulator you prefer. [Elektroda, Mark Harrington, post #21664643]

What goes wrong in the XOR chain at A=B=C=1?

First XOR of A and B outputs 0. The second XOR then passes C as 1, giving y=1. The required output is 0, so XOR fails on 111. [Elektroda, Bob Loy, post #21664649]

Can one switch select among A, B, and C as inputs and still meet the table?

Not by itself. A single selector can’t emulate three independent Boolean inputs. Use the counter‑plus‑decoder idea to step states, or keep three separate inputs. [Elektroda, Bob Loy, post #21664653]
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