VHDL Design for Asynchronous Combination Lock with Four Two-Bit Input Sequence

I have a project that I have to turn in tomorrow. I am having some difficulties. Its my first year at University, I would be really grateful for some help. Here's the question,

This combination lock has a minimum sequence of four two-bit input symbols as the combination and appears to the user as if it is an asynchronous circuit. Actually, it is a synchronous circuit with a fast clock and synchronization of the user inputs. For a given input combination, the circuit goes to a state and cycles there until the input changes to a new symbol; thus, the combination cannot contain consecutive appearances of the same symbol. The lock is locked by using an asynchronous RESET.

It will be designed in VHDL Schematics.
Thank you very much

Hi there, if you could provide a circuit diagram, it would be helpful to understand your circuit.
Or are you being asked to design the circuit ? Or program the software ? Or do you need to create a flowchart ?
(And a picture is worth a thousand words !-)

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I have a feeling, horrible feeling that you need to start with a state diagram "wasnt my strong point either! !" then start with hardware design but untill youve dealt with the state diagrams your going to be in a right fuddle

So first of all must start with this otherwise you simply wont get the hardware right Then as you say possibly wouldnt like to committ myself to this yes a 1 to 4 mux. Demux counter


Hopefully they might have discussed the 4040 and spent considerable time with finite state machines especially detecting sequences

I know I struggled like mad with this and positivley hated this topic

Apparentley the person who started the finite state machines, name I cant remember, but he went mad in the end loopy in other words

Not surprised either Not much consilation I know

Why did you leave the assignment so late

You should have contacted your lecturer straight away if you dont understand this They are normally very helpfull but I do see your point this does seem way over the top fir first year How are you supposed to do this when essentially your not to know about 4040 mux demux nevermind the subject Does seem extremley odd You havent given one of the lectureres a hard time have you? If you have or one of your collegues has that might explain this They dont take to kindly to first year students mucking them around Its what you might call pre installation of eticate and discipline

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Here are some notes for you on finite state machines with example of sequence detectors There are stacks of references on the net A word of advice even if you cant answer the question dont walk in empty handed show your lecturer that you have at least made an attempt otherwise you will be for a blasting

Does sound as though you are heading in the right direction visualising what you have outlined in my head However my applogies but im not paricularly brilliant with your topic I understand some of what your are discussing In fact its strange because this week Im busy doing just this for a fellow friend of mine with respect to demux mux 3to 8 combinations for a control bourd plus cpu So I know this is not an easy task

Hope some of my advice was at least some help to you and best of luck with this It does become more understandible as you move along so give it time and dont give up

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Hi Yigit, I can just offer a little general good advice for a student having problems.

1) Start studying on your set work quickly, so that you will have plenty of time to deal and cope with any difficulties. Plan ahead.

2) As has already been said, go to your tutor quickly for help when you are having problems.

3) As I think you have already realised, if you cannot complete the set piece of work, clearly set out and present all the work you have done so far, in planning and research and design. This can still obtain useful marks or credits for the amount work you have completed.

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