FAQ
TL;DR: Need a 24 V AND with clean logic? Use op-amp/comparator inputs and a driver; "the output current max 50mA" is the reference stat. [Elektroda, Safwan RAJAB, post #21668449]
Why it matters: This FAQ helps engineers choose a safe, noise-robust AND implementation for mixed-voltage signals.
Quick Facts
- CMOS/FET inputs must not exceed their supply voltage; level-shift before the gate. [Elektroda, Safwan RAJAB, post #21668451]
- Zener clamp option: 12 V (or 8 V) with series resistor for 24 V inputs. [Elektroda, Steve Lawson, post #21668454]
- Output drive in the shared design is approx. 50 mA max; use a D313 for more. [Elektroda, Safwan RAJAB, post #21668449]
- Define thresholds, speed, load, and noise needs before picking parts or logic family. [Elektroda, Steve Lawson, post #21668452]
- OP’s supply example was 10 V; plan logic levels and margins accordingly. [Elektroda, Missy Siq, post #21668450]
What’s a safe high-level approach for a 24 V-input AND gate?
Condition each 24 V input with a comparator or op-amp front end, then feed a logic AND or transistor network. This protects inputs, sets thresholds, and provides clean switching. Add an output driver if load current is high. "The perfect electronic way [is] to use Op-amps." [Elektroda, Safwan RAJAB, post #21668451]
Can I just use resistor dividers into 15 V CMOS and amplify the output?
It can work, but respect input limits and noise margins. Ensure divided voltages meet High/Low thresholds across tolerance and temperature. If edges are slow, add hysteresis. Op-amp input conditioning is more robust and repeatable than raw dividers. [Elektroda, Safwan RAJAB, post #21668451]
How do I clamp a 24 V signal down to logic safely?
Use a Zener diode clamp on the input with a series resistor. A 12 V Zener (or 8 V) with proper bias current limits the input and protects the gate. Size the resistor for Zener knee current and power rating. [Elektroda, Steve Lawson, post #21668454]
What specs must I define before picking parts?
Specify input thresholds, signal shape and speed, output load current, source drive capability, and noise environment. These decide logic family, need for hysteresis, and output drivers. Missing these leads to unreliable switching or chatter near thresholds. [Elektroda, Steve Lawson, post #21668452]
Do I need hysteresis if my inputs have slow edges?
Yes. Slow or sloped waveforms can cause multiple toggles without hysteresis. Add Schmitt action in the comparator or gate to clean transitions. This improves immunity in noisy environments and stabilizes switching near threshold. [Elektroda, Steve Lawson, post #21668452]
How much current can the shared solution source at the output?
The referenced design provides about 50 mA max. For higher current, add a transistor like D313 with a heatsink. Verify thermal limits and ensure the driver stage can supply base current. [Elektroda, Safwan RAJAB, post #21668449]
Are relays a good way to implement a high-voltage AND?
Relays can work, but they add inaccuracy, bounce, and slower response. Solid-state front ends with op-amps or comparators give cleaner thresholds and better repeatability. Use relays only when isolation is the priority. [Elektroda, Safwan RAJAB, post #21668451]
Will a simple NMOS-transistor AND at 10 V supply be reliable?
Only if inputs never exceed supply and thresholds are guaranteed. You must set clear High/Low levels and protect the gate oxide. In mixed-voltage systems, add proper level shifting first. [Elektroda, Safwan RAJAB, post #21668451]
What about using a pure 15 V CMOS gate with dividers on the inputs?
Dividers must keep inputs within the gate’s valid range under worst-case conditions. Watch tolerance, temperature, and source impedance. Add buffering or hysteresis if edges are slow or noisy. An op-amp front end remains cleaner. [Elektroda, Missy Siq, post #21668445]
How should I size the Zener clamp resistor?
Choose R so the worst-case input current keeps the Zener above knee current without exceeding its power rating. Also ensure the source can drive it. "Bias just above the knee current" for stability. [Elektroda, Steve Lawson, post #21668454]
What failure modes should I expect without level shifting?
Applying 24 V directly to CMOS/FET inputs can exceed VDD and damage the device. Even brief spikes can punch through the gate oxide, causing latent failure. Always protect inputs first. [Elektroda, Safwan RAJAB, post #21668451]
How do I simulate this before building hardware?
Use Proteus with the shared AND1224.DSN example or build an equivalent testbench. Sweep input voltages, rise times, and temperature. Verify thresholds, propagation delay, and output drive under load. [Elektroda, Safwan RAJAB, post #21668451]
What information should I give the team to get better help?
Provide input waveforms and rise/fall times, exact High/Low thresholds, required frequency, output load type and current, source drive strength, and noise conditions. This speeds accurate recommendations. [Elektroda, Steve Lawson, post #21668452]
Is an 8 V Zener really enough for the clamp?
Yes, if the gate runs at or above 16 V and the output loading supports it. The Zener selection depends on logic supply and desired clamp level. Validate with tolerance and temperature margins. [Elektroda, Steve Lawson, post #21668454]
What supply voltage did the OP target for a simple build?
The OP proposed a 10 V supply for a simple NMOS-based AND. Design thresholds, clamp levels, and drivers with that in mind. Margins shrink at 10 V, so validate carefully. [Elektroda, Missy Siq, post #21668450]
Quick how-to: Build a robust 24 V AND input stage
- Clamp each 24 V input with a Zener and series resistor.
- Buffer with a comparator/op-amp adding hysteresis.
- Feed a logic AND or transistor stage and size the output driver. [Elektroda, Steve Lawson, post #21668454]
