How would you implement this circuit?

See figure with AND gate. Please note input and output voltage requirements.

Hi Missy.
You have asked a very vague question. It loks like your AND gate is not of the usual CMOS ot TTL type due to the high voltages you need it for. This need not be a problem as such but what is needed is information such as "What sped is requires?)

So to make this work (given the voltages), if I use 15V CMOS and then use resistors dividers to bring the voltage down on the input and then take the output and use an opamp to amplify it, would that work? (I was asked to give an implementation for this, so that's why I ask).

Here is your request

I am trying to send the picture for the third time

can you post a jpeg or pdf?

Here you are "jpeg"
the output current max 50mA
If you would more current at the output you can use D313 or similiar to with heat sink
I hope you find your request

Thanks, Rajab. Is this the simplest solution? Could I not simply use a simple AND gate implementation with nmos transistors and then a resistor divider to the the input voltages down? (power supply at 10V)

hello.
the accurate way and perfect is what I sent
You can find other sollutions but have irritations
Cmos or Fet can be used but input voltage musn'tbe over supply voltage
So you can use 2 relays to solve this problem but it woun't be accurate enough
the perfect electronic way to use Op-amps to make the intented operation and that was what I sent
You can be sure using the proteus attached file 'AND1224.DSN' and make the simulation

More information is needed to come up with a proper solution:

1. When you say "swinging voltages", what kind of waveform (square? Or something with a more sloping rise and/or fall function--what is the rise and fall time)? This could determine the need for hysteresis on the input.
2. What are the switching thresholds for the inputs? Knowing that can make a difference on what kind of logic to use, and/or what kind of input conditioning is needed. What is the input high threshold and what is the input low threshold?
3. What is the minimum switching speed/propagation delay and/or the maximum frequency of the input waveforms? Logic family determinant.
4. What will the output be driving? What are the drive current requirements? This will determine logic family and if added driver is required on the output.
5. What is the drive capability of whatever it is that is supplying the inputs to the AND gate? Again this will determine the type of logic and if input conditioning is required and what kind.
6. Will this operate in a noisy environment? What kind of noise immunity is needed?


Or if you can't answer some or all of those questions, then how about a little more information about how this will be used--i.e. what the application will be.

Try a series resistor and 12V zener diode to 24V line in order to regulate the voltage at input gate.

Colin is assuming you're referring to _his_ solution.

But, within that context, he is correct. So, how about a 12V Zener between the 24V signal and the input of the gate [cathode facing toward the 24V signal], with an appropriately valued resistor from the gate input to ground. The value of this resistor will be determined by the driving capability of whatever is supplying the 24V signal and will be limited by both the zener knee current, and the max continuous wattage of the zener.

In this application, though, the conditions should be consistent enough that the zener could effectively be biased at just above the knee current (taking into consideration temperature variation, component tolerances, the amount of stability in that 24 volts (did I forget anything [Colin]?) )

BTW: An 8V zener would suffice, since the supply voltage on the gate will need to be at or above 16V (depending on the output load) anyway, so up to 16V can be applied to the gate (again assuming Colin's solution).