ASK Demodulator

Hi,

I am designing an ASK demodulator for RFID Tags. I have attached the circuit diagram. This is the circuit from IEEE paper.
If you look at the circuit, the first stage is the inverter kind of thing. I didn't get why second NMOS is used for Stage 1. Similarly, the second stage is also inverter with two NMOS. Again, the question why NMOS is used in second stage. But when I checked the output of that stage, it is acting like a latch. The last stage is buffer.

I generated ASK modulated signal and fed as input to the demodulator. I expected that whenever modulated signal is present, demod output is '1' and when no signal is present, it is '0'. To my great surprise, it is always '1'. I tried to give the input by delaying it. So, for the very first time, because of the delay, I could see a logic '0`' at the output. After the delay, there is signal and so the output is logic '1'. Afterwards, though there is no signal, I don't see logic 0 at the output. Its always high. I assumed that the second NMOS at second stage is acting like a latch. Please let me know how can I redesign it. Or is it i have a wrong understanding with the circuit? I have attached the simulated results.

I think you will find Collin i worked harder than you thought I think you will also find i did so non stop regardless of circumstances and i continued to do so despite not being able to afford to go back to studying I taught myself collin I learnt how to teach myself to teach others in the hope that they might just become interested in the real me

Good night Collin

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Really good answers and thanks Mark Harrington.
Thanks!!!