Ultralow Power ADC for 20MHz Input, 20MHz BW, ENOB >4, Power <1mW Architecture Suggestions

Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in
IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a
architecture. I have little experience about this. Kindly help me.

take a look at the faster SAR ones. i'm sure if you scale down the speed of their designs you can achieve your power requirements by scaling everything else appropriately. According to your specs, your upper limit FOM would be:

FOM = power/(2^ENOB x Fc) = 3.125pJ/conv-step

which is on the order of 100 times worse than some IEEE papers I've seen written two years ago. I'd suggest you just find a simple design, adjust it for your frequency requirements, and see where you can scale things down for power.

Thanks for the reply!
I have searched very much but only found two papers that seem appropriate for the requirement.
The requirement about power consumption P< 1mW makes it hard for me.
I attached two papers that I found. Please kindly advise!