Mixed ADC/DAC Problem

[Q] The circuit in the figure represents a counter-based unipolar ADC. When SOC is asserted the counter is reset and clock is enabled so that the counter counts up and the DAC output grows. When the DAC output exceeds the input sample value, the comparator switches from logic 0 to logic 1, disabling the clock and enabling the output buffer by asserting EOC. Assuming all components to be ideal, Vref, DAC output and input to be positive, the maximum error in conversion of the analog sample value is:

(A)directly proportional to Vref
(B) inversely proportional to Vref
(C)independent of Vref
(D)directly proportional to clock frequency

Hi Ansuman,

According to this source the answer is (A) directly proportional to Vref.

Hope it helps,

thank you very much .indeed this would help me lot in my preparation .