How Does ADA2200 Analog Sampling Technology Work Without an ADC?

I am trying to understand how ADA2200 works using the datasheet. I am getting confused because the components specified in it works for digital electronics but it is also said that no ADC is being used and something called Analog Sampling Technology is utilized. It will be very helpful if anyone could help me understand how the entire thing functions and how everything falls into place. 

The datasheet has this:Synchronous demodulators, also known as lock-in amplifiers,
enable accurate measurement of small ac signals in the presence
of noise interference orders of magnitude greater than the signal
amplitude. Synchronous demodulators use phase sensitive
detection to isolate the component of the signal at a specific
reference frequency and phase. Noise at frequencies that are
offset from the reference frequency are easily rejected and do
not significantly impair the measurement.
It's a bit akin to a phase-locked loop (hence Lock-in Amplifier) in that it can pick our a signal of interest (an EEG (brain) signal in medical equipment, or a particular frequency in radioastronomy, for example) out of a lot of noise.  Like phase locked loops (PLLs), they are very good at what they do, but the maths behind their working can be pretty stern stuff.  It is semi-digital in that it shows the use of a small EPROM being used to set up the configuration, but like PLLS the actual processing is all-analog.  There are probably better minds than mine here who could tell you more.

Hi John-It looks like the "secret sauce" is switched capacitor filtering. Here's a Link to their patent that gives a lot more detail.-Rick

Hi John, I'm not sure if this is related, but there are two articles on EETimes that might be of interest:How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICsStellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs

The first article Max mentions, uses an LVDS digital output as a one-bit digital-to-analog converter (DAC) in an analog feedback loop to build a deltasigma analog-to-digital converter (ADC). This can work well. However, the linearity of the resulting ADC is limited by the linearity of the LVDS output as a DAC. In particular, the LVDS rise- and fall-times must be identical and symmetrical to give good linearity averaged over many clock periods of the LVDS output.Except for flash converters, all ADC's are built around DAC's, so the linearity and spurious-free dynamic range (SFDR) are limited by the DAC's.
Deltasigma converter designs were well-discussed in papers and books two decades ago.I built a simple bandpass ADC this way two decades ago, using an ECL flipflop instead of LVDS. Using a 2.4 GHz clock, I was able to receive 7 MHz shortwave broadcast signals through the flipflop.