full bridge inverter with mosfets and associated drain current spikes

Hi everyone. I am currently trying to simulate a full bridge inverter using CPM2-1700-0045B mosfet and ADuM4121_4121-1 gate driver using unipolar switching method. I have a desired output current level and waveform along with desired voltage waveform and voltage level. however, I am seeing spikes in drain current(which is around 36 to 40 amps) in the high side mosfet of the bridge(whereas the peak drain current should be 12Amps-according to load and output voltage) when the low side mosfet is turning on( on leading edge) during which the high side mosfet is completely turned off( the PWM signal can show the if the mosfet is turned on or off). Similar is the case in the low side mosfets. I just cant figure out what is causing these current spikes in the mosfet. I have attached few images that will help get the idea of what I am doing.

The first four waveform shows the drain current for four mosfet of the bridge(AH1,AL1,BH2,BL2), the last two waveforms are the output voltage and current.

You can also see the PWM with the dead time in the next image.

The schematics of my simulation along with the gate driver unit is shown in the last image.

I would highly appreciate any discussions and solutions to this problem.

Thank you.

What is the drain-source capacitance of the MOSFETs? Is this large enough to explain the drain-current spikes?
Ron is much smaller than Roff, so Roff and diode D seem to me to be doing nothing.
Is the output current of the ADuM4121A large enough to charge or discharge the MOSFET gate-to-source capacitance quickly enough?
When a MOSFET turns off, the MOSFET drain-to-gate capacitance will couple the rising drain voltage to the gate, tending to delay the MOSFET turn-off. The MOSFET source inductance will have a similar effect.
I suggest increasing the time during which both upper and lower MOSFETs are off, to see if this reduces the drain-current spikes. Generate a high-time-resolution plot showing the timing relationship between the drain-current spikes and the gate-source voltage, and show it to us.

I was able to decrease the drain current spike in positive side by increasing the R0n to 500ohms and increasing the dead time. However, the spikes on the negative side still exists and it seems that they are happening on falling edge of the pulse train. I cant seem to figure out get rid of those spikes. my gate current is around 800mA which is a bit too low and dont know how to increase my gate current as well. I have uploaded the gate driver circuit for you convinience.

I was able to decrease the drain current spike in positive side by increasing the R0n to 500ohms and increasing the dead time. However, the spikes on the negative side still exists and it seems that they are happening on falling edge of the pulse train. I cant seem to figure out get rid of those spikes. my gate current is around 800mA which is a bit too low and dont know how to increase my gate current as well. I have uploaded the gate driver circuit for you convinience.