Voltage Spikes on MOSFETs in Push-Pull Converter Despite RC Snubber and Decoupling

Hi,
I am designing a push-pull converter.
I attached the schematic, PCB layout, Vgs, Vds and ICs voltage supply.


my problem is that I have got voltage spikes on MOSFETs.
- I have used 2 PCB layers and top layer as a GND plane.

- I have used decoupling capacitors across the ICs.
- I have used RC snubber.
but the problem still exists.

The ringing usually comes about from resonance between the leakage inductance and the FET capacitance, and is hard to avoid, but may be mitigated.Firstly, is it as bad as you think, how are you probing the circuit. The ground on the scope probe could be letting you down, it has to be as short as the probe tip, you have to remove the plastic part of the probe tip and you will see  a metal tubular sleeve near the tip. Supplied with the probe kit should be a  few turns of sprung wire and a ground probe, this slides over the metal sleeve, and you end up with the probe tip and ground adjacent to each other. This minimizes lead inductance and keeps the loop area small.
You of course need to be careful where you probe, as you can add significant ground inductance when making measurement. It often pays to put test points in a circuit that provide appropriate probing points.

How are you driving the FET gates, there being no schematic showing the gate drive, I obviously can't comment, other than to say  you need a high current source to drive the large  gate capacitance,  which has both passive and active components. A push pull transistor arrangement is the simplest method, but there are FET drivers packages as well.While you need to turn the FETs on rapidly to avoid excessive power dissipation, rapidly switching the FETs  exacerbates the parasitic ringing, so there are trade offs.Just a few thoughts, may or may not be relevant,cheers,Richard

Some years ago the late Glen Chenier, a frequent contributor to EETimes and other sites, posted this mystery circuit and asked us to divine its purpose.  It is fairly similar to what you're trying to do.  It has some hefty Zeners across the output transistors whose purpose was to catch these spikes and prevent them destroying the output transistors.  It's possible that you could adopt similar measures for your circuit. There's a fair bit of comment and analysis by other contributors as well.https://www.eetimes.com/author.asp?section_id=36&doc_id=1322956

sorry. I forgot to post the schematic.