Layout design in a board with Ethernet Controller and Connector

Dear forum, recently I started in a new company and a received the task to review a board with ethernet controller W5100 from Wiznet and Ethernet Connector. It has SIM800L module as well ESP8266 uC. I cant give lot of details because confidentialitty.
As I know, for ETH controller and Conn, It has differential signal pairs because ETH interface with RXIN, RXIP and TXON, TXOP. Nobody here in my company really know how to layout it correctly and I have my doubts as well. The guy who route this board did it using auto route (hes mechanical engineer) and here we use Kicad software, but tis not a problem, as up to know wasnt need to buy altium license cause any advanced project (and Im altium user).
However, in this board there are only 2 layers and I dont know if I need to decide and go through 4 layers in this project.
For instance, because this ethernet controller, I attached pictures from this layout and I would like suggestions how to improve it. This layout isnt mine but Ive been improving it draw gnd polygons to tie better connections for ETH controller and Conn. and other gnd points on this board.
I wanna to know if is necessary for top and bottom place gnd plane as was done. As I have ethernet controller and connector, it looks reasonable, but I always have doubt about this gnd plane because this board only have 2 layers and have high speed signals from ethernet controller and connector. If was my design, I should consider to use 4 layers (its more expensive too than 2 layers, so thats my doubt if really need 4 layers or I should keep 2 layers if the only high speed interface is ETH controller/conn and in this way I should consider place it closer? Even it increasing board size, of course...)
Well, here they dont know how to make multilayers and I just know on Altium but I know some theory and rules when go for it... Like for this board with ethernet controller and connector, should be interesting because EMC interference, have a dedicated gnd plane for it and power as soon as besides this ethernet controller I have ESP8266 microcontroller so I have crystal for ethernet and uC, as well clock signal from both, so I dont know if 2 layers gonna be enough for this board work.
What I realized in this layout was about gnd vias for smallest return path which is ok, its good practice for design pcb and via stitching too in order to provide low impedance and short return path, but in Kicad need to place it manually, unfortunetaly. However, I realized a battery charger CI TP4056 between W5100 and RJ45 what I think not good and there are Power Connector too between this path (gnd and +5V). Close to Crystal I realized a connector which is going for AC network 220V. I think its not good as well because noise from AC network of 60hz and its high voltage. There are lot of limited resources compared to Altium but its what I have to work for now. So I would like to have ways to improve it and to resume my questions:
1) Keep 2 layers or go through 4 layers? (1 gnd plane and 1 power plane, 2 signal layers) 2) How to make a correct differential pair for ethernet controller wiznet W5100, I did some serpentine to tune impedance on 50 ohms, and tune differential pair skew to 0mm. 3) Theres a need to use serpentine together with differential pair and which rules I should use, general rules, i find this reference design (https://wizwiki.net/wiki/doku.php?id...hardware:start) 4) What to improve looking for this board? 5) I have SIM800L module, Esp8266 uController and Ethernet interface what to improve looking for this design and its reasonable this way or need to make rework, like place multilayers and its correct to use vias to do differential pair for ETH as was done? Well, whole board was done using auto router, so its complicated and I hope some help from experience hardware engineers here.

Thats it, thanks for advance

Hard to know where to start, you have so many questions.I would strongly suggest you read this PCB layout. It  gives a good summary on how  a PCB should be laid out and the reasoning behind it. Look at the comment on serpentine tracks in the slides.The trick is to make sure that you place the components on the PCB  carefully in the first place to meet the requirements for short track lengths in critical paths, part science, part art. By and large autorouters are a complete waste of time, you invariably end up having to rip a lot of tracks up and manually routing them. Some interactive routers can be useful though. You have to set up rules for each of the critical tracks (or track pairs) if your router allows it before routing them for the best results.There are other problems on the board, acid traps, and the ground pins on the IC seem to have been bridged over  with a ground plane, this will take heat out of the solder lands, and they may not  reflow solder properly. I would suggest that a four layer board is a wize move where you have  high speed differential pairs and EMI to consider. It also simplifies the layout process.Will the unit have to pass radiated and conducted emissions tests. If so, then you should consult with an engineer experienced in the field. The wiznet guide is a good place to start.There is a lot of information on the web, searching on "ethernet pcb layout guidelines" gets a lot of hits, this one from TI, for example, and there are plenty of others. Most do not give specific pcb layouts, since there are many ways of meeting the layout guide specs.Cheers,Richard

Hi RichardThat was a very interesting article in your PCB Layout link.Thanks.

There is a PDF of the slides here, with more detail. The references are worth following up.The average hobbyist will not have to worry too much about these issues, but it is worth knowing about all the same. Anyone doing work with high switching speed logic/processors/fpga  needs to consider it, even if the board clock rates are in the low MHz range.Cheers,Richard 

Hard to know where to start, you have so many questions.
I would strongly suggest you read this PCB layout. It  gives a good summary on how  a PCB should be laid out and the reasoning behind it. Look at the comment on serpentine tracks in the slides.
The trick is to make sure that you place the components on the PCB  carefully in the first place to meet the requirements for short track lengths in critical paths, part science, part art. By and large autorouters are a complete waste of time, you invariably end up having to rip a lot of tracks up and manually routing them. Some interactive routers can be useful though. You have to set up rules for each of the critical tracks (or track pairs) if your router allows it before routing them for the best results.
There are other problems on the board, acid traps, and the ground pins on the IC seem to have been bridged over  with a ground plane, this will take heat out of the solder lands, and they may not  reflow solder properly. 
I would suggest that a four layer board is a wize move where you have  high speed differential pairs and EMI to consider. It also simplifies the layout process.
Will the unit have to pass radiated and conducted emissions tests. If so, then you should consult with an engineer experienced in the field. 
The wiznet guide is a good place to start.
There is a lot of information on the web, searching on "ethernet pcb layout guidelines" gets a lot of hits, this one from TI, for example, and there are plenty of others. Most do not give specific pcb layouts, since there are many ways of meeting the layout guide specs.
Cheers,
Richard
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