How does DRAM interleaved bank access work and how does it reduce memory access time?

How is DRAM with interleaved banks accessed for data
and also how does it helps in reducing the access time?

To read data from a DRAM you must first activate a row within a bank. After the row is open then you can read a column from that row.
Current DRAM technologies have up to 8 banks on a device. The DRAM allows the user to have up to 1 row active in each bank at a given time. Having multiple rows open at a time allows the user to reduce access time by only having to do a column access(read command).
Activation commands and read commands require the user to supply the bank address. This is needed so that the dram can direct the activate or read to the correct bank.