Cmos mirror temp drift?

Hi!

http://i39.tinypic.com/1247rma.gif

This circuit of integrated CMOS transistors are said to have temp error of
+600ppm. Can that be? If so can it be compensated for? Option to bypass
T4 (leaving source open) and route the control (Ica) current externally through
a NPN sink via mosfet drain.

Cheers, Klaus...