How to choose the right w/l dimensions of CMOS binary weighted DAC?

I have a problem of designing a 10 bit DAC. The architecture I use is current steering binary weighted DAC. I cannot attain a ramp output when simulated in SYNOSYS.

Hello,

About your question, at first you should determine the amount of current for each cell according to SNR requirement. and then select the aspect ratio (W/L) of the transistors. actually this is one way to select the W over L . you can find another ways in the reference books such as Data Converters - Franco Maloberti.
If you send me an E-mail, I will send you several papers about that.
my contact E-mail: M.Honarparvar.ee(_at_)gmail.com

Best

It seems the E-mail address can not be seen.
M [dot] Honarparvar [dot] ee [at] gmail [dot] com