How to choose the right w/l dimensions of CMOS binary weighted DAC?

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#1 21661506 17 Mar 2012 09:59

Danielene Mae Caberte Danielene Mae Caberte

Anonymous

Post #1
21661506 17 Mar 2012 09:59

I have a problem of designing a 10 bit DAC. The architecture I use is current steering binary weighted DAC. I cannot attain a ramp output when simulated in SYNOSYS.
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#2 21661507 06 Apr 2012 15:34

Mohammad Honarparvar Mohammad Honarparvar

Anonymous

Post #2
21661507 06 Apr 2012 15:34

Hello,

About your question, at first you should determine the amount of current for each cell according to SNR requirement. and then select the aspect ratio (W/L) of the transistors. actually this is one way to select the W over L . you can find another ways in the reference books such as Data Converters - Franco Maloberti.
If you send me an E-mail, I will send you several papers about that.
my contact E-mail: M.Honarparvar.ee(_at_)gmail.com

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#3 21661508 06 Apr 2012 15:38

Mohammad Honarparvar Mohammad Honarparvar

Anonymous

Post #3
21661508 06 Apr 2012 15:38

It seems the E-mail address can not be seen.
M [dot] Honarparvar [dot] ee [at] gmail [dot] com
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How to choose the right w/l dimensions of CMOS binary weighted DAC?

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