Need help understanding sequential photo-flash trigger circuit

The discussion centers on understanding and improving a sequential photo-flash trigger circuit that currently uses a non-retriggerable one-shot timing element formed by C1 and R3, which ignores subsequent triggers for three seconds. The original circuit requires a negative trigger voltage of approximately -0.4V to -1V. Suggestions include redesigning the circuit using a 4007 CMOS decade counter or modern digital microcontrollers such as PIC16F88 or PIC16F84A to allow sequential triggering of flashes based on camera sync pulses without fixed delays. The microcontroller approach offers programmable control over flash timing, sequence length, and trigger sensitivity, potentially using interrupts and port bit-shifting to drive SCRs controlling the flashes. The trigger voltage from the camera sync terminal was measured at about -0.5V DC, with flash trigger voltages around 3 to 4.5 volts, and a maximum safe trigger voltage of 6 volts to avoid camera damage. A sequential photoflash circuit schematic using a 4017 decade counter and 400V sensitive gate SCRs was provided, triggered by a negative pulse of 1V or more. The presence of a capacitor near the camera sync input is questioned as a debounce element. Due to lack of oscilloscope access, testing will proceed based on the provided schematic, with caution to avoid exceeding safe trigger voltages on the camera sync contacts.
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