How to Read 16 4-bit Data for Image Processing Using VHDL Textio?

I need to read 16 4-bit data using textio in VHDL for image processing. I made a code but it is not working. Please anyone help me.



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity image3 is
generic(m:integer:=4);
port(clk,rst,rd: in std_logic;
data_in: in std_logic_vector(3 downto 0) );
end image3;
architecture behaveral of image3 is
type memory is array (0 to m-1) of std_logic_vector (m-1 downto 0);
type memory_type is array (0 to m-1) of memory;
signal internal: memory_type;
signal rcntr,wcntr: std_logic_vector(1 downto 0);


begin
process(clk,rst)
variable row_inc,column_inc: integer range 0 to m:=0;
begin
if(rst='1') then
for row in 0 to 3 loop
for column in 0 to 3 loop
internal(row)(column)'0');
end loop;
end loop;

row_inc:=0;
column_inc:=0;
rcntr'0');
wcntr'0');

elsif (clk'event and clk='1') then
if rd='1' then
internal(row_inc)(column_inc)