Could any one help me to Initialize RAM from txt file using VHDL ?

I tried to initialize Ram from txt file in VHDL using Modelsim but i found this fatal error during simulation :
Fatal: (vsim-3551) TEXTIO : Read past end of file
how can i solve this problem ?
this is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
entity ram_fil is
Port ( clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (16 downto 1);
din : in STD_LOGIC_VECTOR (8 downto 1);
wen : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (8 downto 1));
end ram_fil;
architecture Behavioral of ram_fil is
type TRam is array(0 to 49105) of std_logic_vector(8 downto 1);
impure function init_bram (ram_file_name : in string) return TRam is
file ramfile : text ;
variable line_read : line;
variable ram_to_return : TRam;
begin
file_open(ramfile,"D:CryptoJust Papermodesim vodesStegocod.txt",READ_MODE);
while not endfile(ramfile) loop
for i in 0 to 49104 loop
readline(ramfile, line_read);
hread(line_read, ram_to_return(i));
end loop;
end loop;
return ram_to_return;
file_close(ramfile);

end function;
signal Ram : TRam := init_bram("D:CryptoJust Papermodesim vodesStegocod.txt");

begin
process (clk)

begin
if (clk'event and clk = '1') then
if (wen = '1') then
Ram(conv_integer(addr))