How Does PowerPC 440 Handle Cache Instructions Like dcbf, dcbt? Structure & Bits

Hi,
I am trying to understand the powerpc 440 instructions and I am unable to understand the cache related instructions. What is the structure of cache entries? In dcbf, dcbt etc, the data block corresponding to EA is searched for in the data cache. How is it done? I mean is a part of EA searched or how is it done I couldnt understand this. Also, it is said that it checks whether it is marked modified or not and then marks it invalid. Where are these modified and valid bits checked?
Please help me I am in urgent need of these.
Thank you.

Ouch caching algorythems. Very very difficult topic to understand this is Master degree studies Personally you dont want to try and understand this in full what you need to know is that cache exists


You will also need to understand the micro architecture as they are discussing the various registers which would also require a very sound knowledge of assembler All your programing needs to be done in assembler

Its purpose is to access memory area on a far quicker basis using address pointers which point to location in ramdom access memory so as to speed up the loading of software or to go back to an originally used part of the operating system, a particular driver for example and load this with high speed rather than having to iterate an entire memory architechure to load that section of code

If you upload the manual I might be able to give you a better explanation Other than this you need to redirect this type of question to someone with a masters degree who majored in caching algorythems

Still being resarched continously highly complicated subject which would also demand that you understand how kernels work with memory dumps and be able to recognise instructions based on pure hex anf binary with associated register

You may have at some point used edlin or possibly tried masm for c plus plus

example below
[code]
mov eax, dwValue
add eax,100
Ret

[/code]

Here is some information which is a good starting point for this topic which may help you

Thank you for the help, Mark. But I need to know about the working of these I mean where are the modified(m) bits and validation(v) bits for each of the cache entry. I have searched a lot. All that I have found out about the m and v bits is that there are two registers DCDBTRL and DCDBTRH for D cache and ICDBTRH and ICDBTRL for I cache that contain these bits. But there are 1k entries and each entry has to be checked for modified and valid bits. This means that each entry should have its own bits for these two bits. In the wiki I found that each cache entry has tag( address ) field, data field and flag field, which is used for any flags to set for specific purpose. But in the user guide for ppc 440, cache entry has tag, set and byte offset fields only. I am attaching the user guide for the same. You can find about cache in chapter 3 and the dcbf ins in pg-254. Please help me if you can.
Thanks in advance.