How to Connect Clock Signals Between FPGA, Memory, and LED Display in Simple Processor

Hello,

I'm confused about how digital circuits in general, and computers in particular, require synchronization via clock pulses, and how this works.

Lets say I'm designing a very simple processor (FPGA BCD converter for example) which is connected to a memory unit. Lets assume that the memory unit is already uploaded with bits to be processed. The FPGA based processor reads from memory and outputs to say a LED display. So how do I plug the clock with these components and make it work???

Thanks.

A clock is really only needed when events need to happen at a certain time interval. In your BCD conversion example (and I assume, because of the LED Display, that you mean a BCD to 7-segment converter), there probably wouldn't be a need for a clock, unless there is some kind of multiplexing going on, and even then, you may not need one.

Typically, when a clock is used, the following scenario is in place:

Some sort of data or state is applied to data lines or inputs of some sort. But, that data or state is not transferred to a next stage until a clock input transitions (either on the rising edge or falling edge or both). That way, the data or state is only transferred at that particular moment.

One example is capturing the outputs of a ripple counter. A ripple counter is a binary counter made from a series of flip-flops with the output of one flip-flop tied to the clock of the next flip-flop. Thus, a count ripples down the counter, but the changes on the outputs do not happen all at once, because of the propagation delays of the flip-flops, thus there can be intermediary states on the output, that if processed, may result in error states. A clock driven parallel register can clean this up and present only correct values on it's output. If the ripple counter is clocked on, say, the falling edge of the clock, and the parallel register is clocked on the rising edge, then the ripple counter will be given a chance to stabilize (a period of one half a clock cycle) before the result is passed to the parallel register's output, and thus, if the frequency of the clock is chosen so that half of it's period is longer than the longest time it takes for the ripple counter to stabalize, the erroneous states are hidden behind the register.

Thanks.

Well it does not look as easy as what logic design courses make it sound to be.
So the clock is merely triggers switches on and off on address/data buss to make sure no intermediate states occur due to propagation delay??? In other words, the clock can switch on/off buss or turn on/off some circuits when it's ready for the job???

No, it doesn't switch it on and off. It triggers a transfer from the input to the output, or from one stage to another. Difficult to explain. Try studying D-type flip-flops. Especially the gate arrangement for making a D-type flip-flop, e.g. using NOR gates or NAND gates. That should give you a "hands on" experience of what a clock is doing.

Why does not my example require a clock to synchronize the operation of reading from memory?

The FPGA will generate address and put it on address bus, then the memory will put the data on data bus connected to the FPGA, which then processes this. It's okay if it's one chunk of bits (= bus bits) but if I'm generating the next address very fast without synch then the mem may put undesired data on the bus while the FPGA still processing the previous bits. Or how can I trigger the next address when it is ready?

You need ideally to go away and do some research on finite state machines That will answer a lot of your questions Also FPGA is not really an ideal place to start what you want to do is learn a small based micro to start with learning about registers, timers, timer interrupts and bit shifting then possibly after dealing with say 8 ,16 , 32 bit micros a bit of 8088 assembler and stacks of c coding then move onto to FPGA

FPGA etc is really quite allot to take in for a beginner with no real understanding of MIPS (Million instructions per second , Binary adders , half adders , booths algorithm etc ) Mux, demux multiplexers which is quite a complicated subject ,TDM, time division multiplexing , FDM, frequency division multiplexing and so forth, ADC , bus types , even believe it or not networking and protocols , asynch and synch serial comms


Lots to learn before you concern yourself with this topic

FPGA is ideally a final goal of what you might want to achieve Its a state you probably reach after 15 years intensive learning and you start to clock on to what’s really happening and how ,excuse the clock on pun used here , rising edge or falling edge

That’s my suggestion to you at this stage its my views only based on how hard and difficult i know this to be possibly the best advice although allot of people may differ in opinions

In fact to be perfectly honest with you Id start with simple access , excell tasks as this will teach you the fundamentals of pointers , tables , iterating through , stack architecture , call and return plus oif course if you dont manage to achive FPGA youve picked a good few skills that are now high in demand for a forgotten generation of people who to be quite honest now desperatly need just these skills alone

Stupid as this may sound these simple basic make embedded technology understandable thats includes simple webpage design with post form methods etc as this also teaches you digital streams , headers , packet information hwo its formed how its transmitted all sots of subjects come into play here and how they work

Not really all that stupid is it when you think about this anymore is it The best years of my life did i spend at Greenwhich UNI I learnt more there than this lot taught me in a decade so god knows what the armed forces would have taught me I shuddder to think

Sorry to tell you that your post does not really make sense. It's like saying before you learn Japanese, you should learn all the other non-Japanese languages.
The example I mentioned is very basic yet I've not got a clear answer from someone who might already implemented something similar. Fair enough.

why do you think that happens time to use your brains here Why indeed , hmmm that’s what knowledge is all about You Yourself asking why and the discussing Its designed to make you think Not us give you all the answers that’s knowledge my friend reasoning asking not of us, but yourself , Truth seeking , www,accesssiviity.com opens 21st this month very interesting people hath i met in my life both invigorating and appealing the real matrix in life I whish her all the best I shall be meeting her in person so interesting has she become , hmmmm

I am crying with laughter and happiness It must be the matrix but never the less you will have to meet the oracle Are you the one I ask ?? Indeed

Maybe it's simplest to think of it in terms of how long it takes your various logic circuits to SETTLE - to reach their final states. In your example, I would guess the FPGA and memory reach their final states maybe a million times faster than the LED display (nanoseconds vs milliseconds).

The key is you don't want to send out clock pulses any faster than your slowest component. The faster components will take care of themselves at the slow clock rate so you don't have to worry about them.

So long as you don't try to update the display faster than it can handle, everything should work.

Thats why I suggested look at finite state machines first " I dont say this to be funny you know " its because he hasent learnt the fundamentals and now hes trying to jump into FPGA without the basics You will end up being so frustrated with this , pulling your hair out , losing your tempers that eventually you will give up and start listening to some of us

START WITH THE BASICS AND GET THAT RIGHT FIRST YOU WILL NOT UNDERSTAND THIS UNTILL YOU DO !!

Try listening for a change make's life that much easier you know instead of wasting years and years and still havent learnt anything at all ( Same old story all over again isnt it Same arguments Same culture Sam rush Same old failures in companies never listen at all far to clever for all of us )

I dont know why you even bother with this lot anymore

Well Mark, different people learn in different ways. I could be wrong, but I got the impression that Shenan Doah might have a "pre-cooked" FPGA algorithm ready to load. Even if not, sequential logic is definitely harder than basic combinational logic, which the questioner may already have mastered.

I once worked for a guy who made incredible rack-mounted electric guitar effects. He told me that when he started out, he "didn't know an op amp from a hole in the ground."

As I said, different people learn in different ways. They can't all march to your drummer, Mark.