How to Reduce Power and Delay in Full Swing Full Adder Using Cadence 6.1.4.500?

I am doing my mini project. This is a new full swing full adder based on a logic approach in cadence tool(6.1.4.500 version). I already completed drawing schematics everything that required for this and I also verified the truth table. Everything is satisfying but coming to the comparison table while comparing the power and delay terms, I am getting more power and delay compared to the other previous circuits. So,i request you to please suggest something to overcome this problem and also the changes to be done to this to make this project as an application oriented . Attached herewith is my project paper in pdf format.

Thanks in advance...

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