Sizing of SRAM design

I am designing single ported SRAM with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits each so muxes would also be required. How do I size each of them? All I know is about sizing 6T cell to minimum so it saves area.