Hi all,
I am using Assura to run DRC on one of the HV inverter cells in the standard cell library CORELIB_HV in the ams h35b3 technology and am recieving the errors shown in the attached document.
The first error I understand to actually be an ERC error and to be a result of a missing or insuffcient contact between the substrate and gnd.
The second error I can fix by increasing the width of the DNTUB layer to 14.
And the list goes on... I am wondering if anyone has come across this issue or can provide some feedback on where I have gone wrong in running DRC. Since this is a standard cell, it should pass DRC issue free.
I am using Assura to run DRC on one of the HV inverter cells in the standard cell library CORELIB_HV in the ams h35b3 technology and am recieving the errors shown in the attached document.
The first error I understand to actually be an ERC error and to be a result of a missing or insuffcient contact between the substrate and gnd.
The second error I can fix by increasing the width of the DNTUB layer to 14.
And the list goes on... I am wondering if anyone has come across this issue or can provide some feedback on where I have gone wrong in running DRC. Since this is a standard cell, it should pass DRC issue free.
