Hi, am trying to build a JK Flip flop using NAND gate, but the circuit i build is not simulating, i

Hi, am trying to build a JK Flip flop using NAND gate, but the circuit i build is not simulating, i need a help with corrections please 

Try thinking through your circuit manually as the clock rises, and as the clock falls, and compare your thoughts to the simulation. Follow the clock edge through the gates, one gate at a time. Are you trying to build a JK flipflop that changes state on the rising edge of the clock, or on the falling edge?

You need some type of temporary storage to hold the old state while the main flipflop is changed to the new state. One common way to do this in CMOS is to use two cascaded latches, as in a master-slave flipflop. Look carefully at propagation delays and gate thresholds as the clock changes state. In TTL, capacitive delay is often used, requiring that the clock rises and falls sufficiently quickly.

Ephrem, you could do worse than to look up a TTL or CMOS JK flipflop data sheet, that will give the diagram of the gates used.  You will normally have to do a bit of substitution and modification to construct the circuit from NAND gates, but it's a good learning experience.

Part of the problem could be that there are no current limiting resistors in series with the LED's.  This may keep the output voltage from going high enough to be recognized as a logic "1".
-Rick

I am not clear what it is you are asking, is it if the JK flip flop  correct logic wise, or why is the simulator not working, or both.If you are using a logic simulator, which one is it?  I assume if you are using one that the LEDs are simulated indicators.Looking at your circuit, which appears to be correct for a basic JK FF, you have to be aware from it that the J and K inputs have various states. Check the truth table and set up the J and K inputs according to it and see what happens. 
This particular circuit has problems associated with a condition called "race", so an additional stage is used to change the state on an edge, rather than a logic level.Cheers,
Richard

Hi Richard thanks for the reply 
here is the truth table 

OK, so you have the truth table, now with the logic inputs indicated in the schematic, J and K both 0, what does the truth table say the output Q and *Q will be?Try changing  input states J and K according to the truth table and see if the corresponding outputs on Q and *Q change according to the input states when clocked.If you are having problems with the simulator, try some simpler arrangement of gates to see if you can get them to work properly first. Some simulators will possibly have a problem with cross coupled gates (latches) , in real logic devices propagation delay and/or some form of initialization (pull up, pull downs, or reset circuitry) will ensure that latches will start in an appropriate state. Cheers,Richard