How does a circuit determine the number of clock cycles required for operation?

Hi guys, there's some circuit (doesn't matter what's exactly) which would require three clocks or double clock cycle to be operated properly .. my question is there inside the circuit a counter which count how many clocks does the circuit interface? it's really weird how does the circuit know she got two or three cycle clocks in order to be operated properly?! 

thanks !

If the logic is pipelined, the result is simply delayed by the number of pipeline stages.  Whoever is using the logic may need to know how many clock cycles the result is delayed.

If the logic is not pipelined, there does need to be some sort of counter that's part of the logic design.  It's not magic: there needs to be explicit logic. Sometimes such a logic block has "handshaking" signals to indicate when it's ready for new inputs and/or when a new result is available.

Hi there -- I'm not quite sure what you are asking, but here are a few thoughts. We typically think about a clock signal as looking something like the following:So this has got a 50% duty cycle, or a 1:1 mark-space ratio, which means that the amount of time it's at a logic 1 is the same as the time it's at a logic 0 (we'll come back to this in a moment).In his response, John was talking about pipelining. I think the type he's thinking of is like the following, where we have a series of registers driven by the same clock:
In this case, the first clock will load the value on data-in into the first register. The next clock will load the output from the first register into the second register -- at the same time it will load the new value on data-in into the first register. The next clock will load the output from the second register into the third register -- at the same time it will load the output from the first register into the second register -- at the same time it will load the new value on data-in into the first register. I always think of this part like "priming a water pump" -- once the pipeline is fully loaded, each new clock (pump of the handle) will cause the data to be "passed down the line" -- sort of like a chain pf people passing buckets of water to each other.However, I get the impression that this is not what you were talking/asking about. Another way to present a clock would be as follows:
In this case, the clock is a logic 1 for only a short time compared to the amount of time its a logic 0. So long as the width of the 1 meets the minimum clock pulse width requirements of the registers, this would behave exactly like our first clock.The reason I mention this is that some of the early microprocessors had clock generators that output a single-phase clock as shown above; others used 2-phase clocks, and others used 4-phase clocks as illustrated below:
If you think of our register circuit shown above, we could use the first clock to load the first register, the second clock to load the second register, the third clock to load the third register, and so on.The early microprocessors didn't do things in quite this way, but the idea is similar -- you would use one of the clock phases to control some of the registers/functions, and another phase to control different registers/functions. You didn't need a counter inside the microprocessor -- the various clock phases where hardwired to the thinks they were controlling (the clock generator itself might employ some sort of counter function to generate the four phases).Does this answer your question?