How Does the Clock Move Instructions Through Each Stage in MIPS Single-Cycle Datapath?

Hi guys, about datapath in MIPS(one cycle datapath) I understand everything and every step how datapath of MIPS works, but HOW clock is enable to move my instruction one stage/step forward every one clock cycle? can anyone please please illustrate for me how clock is enable to move my instruction one step forward at each stage? for example at first clock my instruction would be at first stage, at second step ..my instruction will move to second step ..etc , how actually clock does that? what's not entering my head is how clock moving instruction at every cycle one step forward?!!!!! 

I will thank anyone who can please help me to understand how clock has the ability to forward at every cycle my instruction ..it's like magic!

You understand the data path's pipeline.  At each clock the results of each stage of the pipeline become the inputs of the next stage of the pipeline.In parallel with the data pipeline there is an instruction pipeline.  Each stage of the instruction pipeline has bits to tell the data path what to do during that stage.  For example, there may an execution stage where the data path performs an arithmetic or logic operation like ADD, SUB, AND, OR, or XOR using an Arithmetic/Logic Unit (ALU).  There must be a corresponding stage in the instruction pipeline that has bits that tell the ALU which operation to perform.  These bits are decoded from machine-language instructions.
Each data pipeline stage has input registers that hold the input data for that stage.  The corresponding instruction pipeline stage has an input register with bits that tell the data stage what to do.  At the end of each clock cycle, each stage of the data pipeline clocks the data result into the next stage's input registers.  Similarly, each stage of the instruction pipeline clocks bits into the next instruction stage's input register to tell the next stages what to do.
Each  instruction pipeline register must have enough bits to tell the remaining stages what to do.  For example, some bits may specify the destination register of the final result and need to be carried from stage to stage until you reach the stage that writes back the result.  As the data and instructions flow through the pipeline, instruction bits that are no longer needed can be discarded.
Hope this helps!

So we are saying that implicitly the instruction moves forward at each clock cycle but what exactly happened is like what you said here "At each clock the results of each stage of the pipeline become the inputs of the next stage of the pipeline." .....  I mean moving output of first stage to input of second stage is implicitly forwarding the data between stages .... right?! 

I know what's datapath means but I just would like to understand how clock is letting instructions moves forward at each cycle .. 

But how the second stage is working in the second cycle clock? lets assume I send 10 clocks within specific frequency then the first clock which has been absorbed on the first stage will complete to the second stage so the first clock is also absorbed in the second stage .. why we are not saying it's working in first clock cycle? is the first clock cycle gone after he passed from the first stage?!I'm getting confused if first clock was passed from first stage then the same first clock will complete to the second stage and then will operate it .. so why we are saying that the second stage needs two clocks to be operated?!

to be more clear lets take two stages of IF and ID , if I send three clock cycles to IF then IF will operate at first clock and that's first clock will continue to the second stage so also the second stage will be operated by first clock , if I send second clock to IF then it will be operated again and second clock will go to second stage and will operate it also .. so how we determine that first stage will need one cycle to be operated properly and second stage needed two clock cycles to be operated properly?! and third stage needs three clocks cycles to be operated properly .. how is that going and why we are determining that? I'm totally not getting the idea behind the relation between number of clock to stage's number!

Ryan wrote: I mean moving output of first stage to input of second stage is implicitly forwarding the data between stages .... right?! Yes, that is correct.  I like to think of a pipeline as blocks of combinational (unclocked) logic separated by pipelining registers.  The output of pipeline stage 1 gets clocked into its output register at the end of the clock cycle 1 and becomes the input to stage 2 at the beginning of clock cycle 2.

Let's say you have broken the execution of an instruction into N steps which are performed by an N-stage pipeline.  It takes N clock cycles to run an instruction through N stages.  That is, it takes N cycles to complete execution of each instruction.All N stages can be working at the same time.  However, each stage is working on a different instruction.  Ideally the pipeline is working on N instructions at the same time.  Each clock cycle a new instruction enters the pipeline and each clock cycle the oldest instruction completes and vanishes from the pipeline.Let's say you're executing three instructions A, B, and C:During clock cycle 1, instruction A step 1 is performed by pipeline stage 1.
At the beginning of clock cycle 2, the result of instruction A step 1 is passed to stage 2 and instruction B enters stage 1.
During clock cycle 2, instruction B step 1 is performed by stage 1 and simultaneously instruction A step 2 is performed by stage 2.
At the beginning of clock cycle 3, the result of instruction A step 2 is passed to stage 3, the result of instruction B step 1 is passed to stage 2 and instruction C enters stage 1.During clock cycle 3, all three stages are working: stage 1 on instruction C step 1, stage 2 on instruction B step 2, and stage 3 on instruction A step 3.
If N = 3, at the end of clock cycle 3 instruction A is complete and vanishes from the pipeline.Hope this helps.

In most pipelines, each stage of the pipeline takes one clock cycle.  To achieve this, the logic required to execute an instruction is broken into pipeline stages of approximately equal length.  The slowest stage determines the clock cycle. 
(Instruction fetch may take extra clock cycles, for example if there is a cache miss or a page fault.  In this case the pipeline has to pause and wait for the instruction to be fetched from slower memory.  But let's consider basic pipelining first.)

"how we determine that first stage will need one cycle to be operated
properly and second stage needed two clock cycles to be operated
properly?! and third stage needs three clocks cycles to be operated
properly" The first stage takes one clock to operate properly. The second stage takes one clock to operate properly, but that operation is DELAYED ONE CLOCK to use the output of the first stage. The third stage takes one clock to operate properly, but that operation is DELAYED TWO CLOCKS to use the output of the second stage.Do you understand how D flipflops work? A register is built from D flipflops.Do you know how shift registers work? A shift register is the simplest possible pipeline, so understanding shift registers will help you understand pipelines.
I suggest you print a few copies of your illustration. On the first copy, write down what is where after the first clock. On the second copy, write down what is where after the second clock. On the third copy, write down what is where after the third clock. And so on...