How to adjust PCIE signals using Hyperlynx S- Parameter report?

I’m using Hyperlynx SI (MentorGraphic) for Signal Integrity test for PCIE GEN 1 Tx Rx & Clk signals. I imported Altium designed layout file to Hyperlynx. This signals (Tx, Rx, Clk) don’t pass S – Parameters when I run Serdes Batch Wizard. But it pass Channel Verification.

1) What are the changes should I do to design to pass S Parameters. How can I figure out the things need to be done using S – Parameter report?
2) Is it possible to do those changes to imported Altium design directly?
3) Why doesn’t it pass S – Parameters and but pass channel verification?

Regards,
John.

To help other people, please send more info about MentorGraphic. I think that the option is not implemented.

MentorGraphics  sells a number of high-end electronics CAD tools. Their signal integrity tool is Hyperlynx.https://www.mentor.com/pcb/hyperlynx/I've
used Hyperlynx and found it to be very powerful and accurate.
Unfortunately, there is often a question (as in this case) of how to
adjust the circuit, layout or parameters to improve the result.The
answer to the original question has more to do with how to set up PCIE
than the use of Hyperlynx. Unfortunately, I don't know enough about PCIE
to begin to answer this other than to check the data sheets, reference
guides and forums specific to the parts involved.