Hello everyone,
I am working with TMDSEVM6657 and DAC80504EVM and I would like to connect them via SPI interface.
While learning about the SPI interface of TMDSEVM6657LS board using SPI User Guide for Keystone devices I have understood that (as also one of the TI e2e engineers suggested):
The SPI master can automatically insert a delay of between 2 and 65 SPI module clock cycles between transmissions. This delay is controlled by the WDELAY field in the SPI data format register n (SPIFMTn) and is enabled by setting the WDEL bit in the SPI transmit data register (SPIDAT1) to 1. The WDELAY period begins when the T2EDELAY period terminates (if T2E delay period is enabled) or when the T2CDELAY period terminates (if T2E delay period was disabled and T2C delay period was enabled) or when the master deasserts SPISCS[n] (if T2E and T2C delay periods are disabled). If a transfer is initiated by writing a 32-bit value to SPIDAT1, then the new values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used; otherwise, the old values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used. The WDELAY delay period is specified by: Maximum duration of WDELAY period = SPIFMTn.WDELAY + 2 (SPI module clock cycles).
I am interested to know is there a possibility to have a continuous SPI transfer using this board, considering that I want to use it to communicate to DAC80504EVM (which expects continuous stream of 24 bits). As far as my understanding goes SPI transfer using c6657 enables transfers up to 16 bits at a time. Therefore, in order to send continuous stream of 24 bits, I would need to be able to maintain continuous SPI transfer from c6657.
If we take a look at the paragraph above, it seems like the smallest delay between the transfers is 2 SPI module clock cycles, and that it is something that cannot be avoided (WDELAY period = 0 + 2 (SPI module clock cycles)). In that case, the SPI communication between the TMDSEVM6657LS and the converter would not be possible.
Is that correct? I would very much appreciate it if anyone could support me with this issue. I am trying to build this system as part of my Master Thesis, and enabling the communication is a very important part of it. Also, it would be a waste not to be able to use the equipment I already bought.
Please, let me know what you think.
I already tried reaching out to e2e forum couple of days ago, but they still haven't been able to provide me with the answer.
Kind regards,
Dejana
I am working with TMDSEVM6657 and DAC80504EVM and I would like to connect them via SPI interface.
While learning about the SPI interface of TMDSEVM6657LS board using SPI User Guide for Keystone devices I have understood that (as also one of the TI e2e engineers suggested):
The SPI master can automatically insert a delay of between 2 and 65 SPI module clock cycles between transmissions. This delay is controlled by the WDELAY field in the SPI data format register n (SPIFMTn) and is enabled by setting the WDEL bit in the SPI transmit data register (SPIDAT1) to 1. The WDELAY period begins when the T2EDELAY period terminates (if T2E delay period is enabled) or when the T2CDELAY period terminates (if T2E delay period was disabled and T2C delay period was enabled) or when the master deasserts SPISCS[n] (if T2E and T2C delay periods are disabled). If a transfer is initiated by writing a 32-bit value to SPIDAT1, then the new values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used; otherwise, the old values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used. The WDELAY delay period is specified by: Maximum duration of WDELAY period = SPIFMTn.WDELAY + 2 (SPI module clock cycles).
I am interested to know is there a possibility to have a continuous SPI transfer using this board, considering that I want to use it to communicate to DAC80504EVM (which expects continuous stream of 24 bits). As far as my understanding goes SPI transfer using c6657 enables transfers up to 16 bits at a time. Therefore, in order to send continuous stream of 24 bits, I would need to be able to maintain continuous SPI transfer from c6657.
If we take a look at the paragraph above, it seems like the smallest delay between the transfers is 2 SPI module clock cycles, and that it is something that cannot be avoided (WDELAY period = 0 + 2 (SPI module clock cycles)). In that case, the SPI communication between the TMDSEVM6657LS and the converter would not be possible.
Is that correct? I would very much appreciate it if anyone could support me with this issue. I am trying to build this system as part of my Master Thesis, and enabling the communication is a very important part of it. Also, it would be a waste not to be able to use the equipment I already bought.
Please, let me know what you think.
I already tried reaching out to e2e forum couple of days ago, but they still haven't been able to provide me with the answer.
Kind regards,
Dejana
